xref: /freebsd/sys/contrib/device-tree/Bindings/soc/ti/ti,j721e-system-controller.yaml (revision 9978553d0199e7ec0bdd1c44fc7f6c7b0c11e43b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/soc/ti/ti,j721e-system-controller.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: TI J721e System Controller Registers R/W
9
10description: |
11  This represents the Control Module registers (CTRL_MMR0) on the SoC.
12  System controller node represents a register region containing a set
13  of miscellaneous registers. The registers are not cohesive enough to
14  represent as any specific type of device. The typical use-case is
15  for some other node's driver, or platform-specific code, to acquire
16  a reference to the syscon node (e.g. by phandle, node path, or
17  search using a specific compatible value), interrogate the node (or
18  associated OS driver) to determine the location of the registers,
19  and access the registers directly.
20
21maintainers:
22  - Kishon Vijay Abraham I <kishon@kernel.org>
23  - Roger Quadros <rogerq@kernel.org>
24
25properties:
26  compatible:
27    items:
28      - enum:
29          - ti,am654-system-controller
30          - ti,j7200-system-controller
31          - ti,j721e-system-controller
32          - ti,j721s2-system-controller
33      - const: syscon
34      - const: simple-mfd
35
36  reg:
37    maxItems: 1
38
39  "#address-cells":
40    const: 1
41
42  "#size-cells":
43    const: 1
44
45  ranges: true
46
47patternProperties:
48  # Optional children
49  "^mux-controller@[0-9a-f]+$":
50    type: object
51    description:
52      This is the SERDES lane control mux.
53
54  "^clock-controller@[0-9a-f]+$":
55    type: object
56    $ref: /schemas/clock/ti,am654-ehrpwm-tbclk.yaml#
57    description:
58      Clock provider for TI EHRPWM nodes.
59
60  "phy@[0-9a-f]+$":
61    type: object
62    $ref: /schemas/phy/ti,phy-gmii-sel.yaml#
63    description:
64      The phy node corresponding to the ethernet MAC.
65
66  "^chipid@[0-9a-f]+$":
67    type: object
68    $ref: /schemas/hwinfo/ti,k3-socinfo.yaml#
69    description:
70      The node corresponding to SoC chip identification.
71
72  "^pcie-ctrl@[0-9a-f]+$":
73    type: object
74    description:
75      The node corresponding to PCIe control register.
76
77  "^clock@[0-9a-f]+$":
78    type: object
79    $ref: /schemas/soc/ti/ti,am654-serdes-ctrl.yaml#
80    description:
81      This is the Serdes Control region.
82
83  "^dss-oldi-io-ctrl@[0-9a-f]+$":
84    type: object
85    $ref: /schemas/mfd/syscon.yaml#
86    description:
87      This is the DSS OLDI CTRL region.
88
89required:
90  - compatible
91  - reg
92  - "#address-cells"
93  - "#size-cells"
94  - ranges
95
96additionalProperties: false
97
98examples:
99  - |
100    scm_conf: scm-conf@100000 {
101        compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
102        reg = <0x00100000 0x1c000>;
103        #address-cells = <1>;
104        #size-cells = <1>;
105        ranges;
106
107        serdes_ln_ctrl: mux-controller@4080 {
108            compatible = "mmio-mux";
109            reg = <0x00004080 0x50>;
110
111            #mux-control-cells = <1>;
112            mux-reg-masks =
113                <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
114                <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
115                <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
116                <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
117                <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
118                /* SERDES4 lane0/1/2/3 select */
119        };
120
121        clock-controller@4140 {
122            compatible = "ti,am654-ehrpwm-tbclk";
123            reg = <0x4140 0x18>;
124            #clock-cells = <1>;
125        };
126
127        chipid@14 {
128            compatible = "ti,am654-chipid";
129            reg = <0x14 0x4>;
130        };
131
132        pcie0_ctrl: pcie-ctrl@4070 {
133            compatible = "ti,j784s4-pcie-ctrl", "syscon";
134            reg = <0x4070 0x4>;
135        };
136    };
137...
138