xref: /freebsd/sys/contrib/device-tree/Bindings/soc/qcom/qcom,gsbi.yaml (revision d5b0e70f7e04d971691517ce1304d86a1e367e2e)
1*d5b0e70fSEmmanuel Vadot# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2*d5b0e70fSEmmanuel Vadot%YAML 1.2
3*d5b0e70fSEmmanuel Vadot---
4*d5b0e70fSEmmanuel Vadot$id: http://devicetree.org/schemas/soc/qcom/qcom,gsbi.yaml#
5*d5b0e70fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml#
6*d5b0e70fSEmmanuel Vadot
7*d5b0e70fSEmmanuel Vadottitle: Qualcomm General Serial Bus Interface (GSBI)
8*d5b0e70fSEmmanuel Vadot
9*d5b0e70fSEmmanuel Vadotmaintainers:
10*d5b0e70fSEmmanuel Vadot  - Andy Gross <agross@kernel.org>
11*d5b0e70fSEmmanuel Vadot  - Bjorn Andersson <bjorn.andersson@linaro.org>
12*d5b0e70fSEmmanuel Vadot  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
13*d5b0e70fSEmmanuel Vadot
14*d5b0e70fSEmmanuel Vadotdescription:
15*d5b0e70fSEmmanuel Vadot  The GSBI controller is modeled as a node with zero or more child nodes, each
16*d5b0e70fSEmmanuel Vadot  representing a serial sub-node device that is mux'd as part of the GSBI
17*d5b0e70fSEmmanuel Vadot  configuration settings.  The mode setting will govern the input/output mode
18*d5b0e70fSEmmanuel Vadot  of the 4 GSBI IOs.
19*d5b0e70fSEmmanuel Vadot
20*d5b0e70fSEmmanuel Vadot  A GSBI controller node can contain 0 or more child nodes representing serial
21*d5b0e70fSEmmanuel Vadot  devices.  These serial devices can be a QCOM UART, I2C controller, spi
22*d5b0e70fSEmmanuel Vadot  controller, or some combination of aforementioned devices.
23*d5b0e70fSEmmanuel Vadot
24*d5b0e70fSEmmanuel Vadotproperties:
25*d5b0e70fSEmmanuel Vadot  compatible:
26*d5b0e70fSEmmanuel Vadot    const: qcom,gsbi-v1.0.0
27*d5b0e70fSEmmanuel Vadot
28*d5b0e70fSEmmanuel Vadot  '#address-cells':
29*d5b0e70fSEmmanuel Vadot    const: 1
30*d5b0e70fSEmmanuel Vadot
31*d5b0e70fSEmmanuel Vadot  cell-index:
32*d5b0e70fSEmmanuel Vadot    $ref: /schemas/types.yaml#/definitions/uint32
33*d5b0e70fSEmmanuel Vadot    description:
34*d5b0e70fSEmmanuel Vadot      The GSBI index.
35*d5b0e70fSEmmanuel Vadot
36*d5b0e70fSEmmanuel Vadot  clocks:
37*d5b0e70fSEmmanuel Vadot    maxItems: 1
38*d5b0e70fSEmmanuel Vadot
39*d5b0e70fSEmmanuel Vadot  clock-names:
40*d5b0e70fSEmmanuel Vadot    const: iface
41*d5b0e70fSEmmanuel Vadot
42*d5b0e70fSEmmanuel Vadot  qcom,crci:
43*d5b0e70fSEmmanuel Vadot    $ref: /schemas/types.yaml#/definitions/uint32
44*d5b0e70fSEmmanuel Vadot    description:
45*d5b0e70fSEmmanuel Vadot      CRCI MUX value for QUP CRCI ports.  Please reference
46*d5b0e70fSEmmanuel Vadot      include/dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
47*d5b0e70fSEmmanuel Vadot
48*d5b0e70fSEmmanuel Vadot  qcom,mode:
49*d5b0e70fSEmmanuel Vadot    $ref: /schemas/types.yaml#/definitions/uint32
50*d5b0e70fSEmmanuel Vadot    description:
51*d5b0e70fSEmmanuel Vadot      MUX value for configuration of the serial interface.  Please reference
52*d5b0e70fSEmmanuel Vadot      include/dt-bindings/soc/qcom,gsbi.h for valid mux values.
53*d5b0e70fSEmmanuel Vadot
54*d5b0e70fSEmmanuel Vadot  '#size-cells':
55*d5b0e70fSEmmanuel Vadot    const: 1
56*d5b0e70fSEmmanuel Vadot
57*d5b0e70fSEmmanuel Vadot  syscon-tcsr:
58*d5b0e70fSEmmanuel Vadot    $ref: /schemas/types.yaml#/definitions/phandle
59*d5b0e70fSEmmanuel Vadot    description:
60*d5b0e70fSEmmanuel Vadot      Phandle of TCSR syscon node.Required if child uses dma.
61*d5b0e70fSEmmanuel Vadot
62*d5b0e70fSEmmanuel Vadot  ranges: true
63*d5b0e70fSEmmanuel Vadot
64*d5b0e70fSEmmanuel Vadot  reg:
65*d5b0e70fSEmmanuel Vadot    maxItems: 1
66*d5b0e70fSEmmanuel Vadot
67*d5b0e70fSEmmanuel VadotpatternProperties:
68*d5b0e70fSEmmanuel Vadot  "spi@[0-9a-f]+$":
69*d5b0e70fSEmmanuel Vadot    type: object
70*d5b0e70fSEmmanuel Vadot    $ref: /schemas/spi/qcom,spi-qup.yaml#
71*d5b0e70fSEmmanuel Vadot
72*d5b0e70fSEmmanuel Vadot  "i2c@[0-9a-f]+$":
73*d5b0e70fSEmmanuel Vadot    type: object
74*d5b0e70fSEmmanuel Vadot    $ref: /schemas/i2c/qcom,i2c-qup.yaml#
75*d5b0e70fSEmmanuel Vadot
76*d5b0e70fSEmmanuel Vadot  "serial@[0-9a-f]+$":
77*d5b0e70fSEmmanuel Vadot    type: object
78*d5b0e70fSEmmanuel Vadot    $ref: /schemas/serial/qcom,msm-uartdm.yaml#
79*d5b0e70fSEmmanuel Vadot
80*d5b0e70fSEmmanuel Vadotrequired:
81*d5b0e70fSEmmanuel Vadot  - compatible
82*d5b0e70fSEmmanuel Vadot  - cell-index
83*d5b0e70fSEmmanuel Vadot  - clocks
84*d5b0e70fSEmmanuel Vadot  - clock-names
85*d5b0e70fSEmmanuel Vadot  - qcom,mode
86*d5b0e70fSEmmanuel Vadot  - reg
87*d5b0e70fSEmmanuel Vadot
88*d5b0e70fSEmmanuel VadotadditionalProperties: false
89*d5b0e70fSEmmanuel Vadot
90*d5b0e70fSEmmanuel Vadotexamples:
91*d5b0e70fSEmmanuel Vadot  - |
92*d5b0e70fSEmmanuel Vadot    #include <dt-bindings/clock/qcom,gcc-msm8960.h>
93*d5b0e70fSEmmanuel Vadot    #include <dt-bindings/interrupt-controller/arm-gic.h>
94*d5b0e70fSEmmanuel Vadot    #include <dt-bindings/soc/qcom,gsbi.h>
95*d5b0e70fSEmmanuel Vadot
96*d5b0e70fSEmmanuel Vadot    gsbi@12440000 {
97*d5b0e70fSEmmanuel Vadot        compatible = "qcom,gsbi-v1.0.0";
98*d5b0e70fSEmmanuel Vadot        reg = <0x12440000 0x100>;
99*d5b0e70fSEmmanuel Vadot        cell-index = <1>;
100*d5b0e70fSEmmanuel Vadot        clocks = <&gcc GSBI1_H_CLK>;
101*d5b0e70fSEmmanuel Vadot        clock-names = "iface";
102*d5b0e70fSEmmanuel Vadot        #address-cells = <1>;
103*d5b0e70fSEmmanuel Vadot        #size-cells = <1>;
104*d5b0e70fSEmmanuel Vadot        ranges;
105*d5b0e70fSEmmanuel Vadot
106*d5b0e70fSEmmanuel Vadot        syscon-tcsr = <&tcsr>;
107*d5b0e70fSEmmanuel Vadot        qcom,mode = <GSBI_PROT_I2C_UART>;
108*d5b0e70fSEmmanuel Vadot
109*d5b0e70fSEmmanuel Vadot        serial@12450000 {
110*d5b0e70fSEmmanuel Vadot            compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
111*d5b0e70fSEmmanuel Vadot            reg = <0x12450000 0x100>,
112*d5b0e70fSEmmanuel Vadot                  <0x12400000 0x03>;
113*d5b0e70fSEmmanuel Vadot            interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
114*d5b0e70fSEmmanuel Vadot            clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
115*d5b0e70fSEmmanuel Vadot            clock-names = "core", "iface";
116*d5b0e70fSEmmanuel Vadot        };
117*d5b0e70fSEmmanuel Vadot
118*d5b0e70fSEmmanuel Vadot        i2c@12460000 {
119*d5b0e70fSEmmanuel Vadot            compatible = "qcom,i2c-qup-v1.1.1";
120*d5b0e70fSEmmanuel Vadot            reg = <0x12460000 0x1000>;
121*d5b0e70fSEmmanuel Vadot            pinctrl-0 = <&i2c1_pins>;
122*d5b0e70fSEmmanuel Vadot            pinctrl-1 = <&i2c1_pins_sleep>;
123*d5b0e70fSEmmanuel Vadot            pinctrl-names = "default", "sleep";
124*d5b0e70fSEmmanuel Vadot            interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
125*d5b0e70fSEmmanuel Vadot            clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
126*d5b0e70fSEmmanuel Vadot            clock-names = "core", "iface";
127*d5b0e70fSEmmanuel Vadot            #address-cells = <1>;
128*d5b0e70fSEmmanuel Vadot            #size-cells = <0>;
129*d5b0e70fSEmmanuel Vadot
130*d5b0e70fSEmmanuel Vadot            status = "disabled"; /* UART chosen */
131*d5b0e70fSEmmanuel Vadot        };
132*d5b0e70fSEmmanuel Vadot    };
133