1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: GENI Serial Engine QUP Wrapper Controller 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 12description: | 13 Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper 14 is a programmable module for supporting a wide range of serial interfaces 15 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial 16 Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP 17 Wrapper controller is modeled as a node with zero or more child nodes each 18 representing a serial engine. 19 20properties: 21 compatible: 22 enum: 23 - qcom,geni-se-qup 24 - qcom,geni-se-i2c-master-hub 25 26 reg: 27 description: QUP wrapper common register address and length. 28 maxItems: 1 29 30 clock-names: 31 minItems: 1 32 maxItems: 2 33 34 clocks: 35 minItems: 1 36 maxItems: 2 37 38 "#address-cells": 39 const: 2 40 41 "#size-cells": 42 const: 2 43 44 ranges: true 45 46 interconnects: 47 maxItems: 1 48 49 interconnect-names: 50 const: qup-core 51 52 iommus: 53 maxItems: 1 54 55required: 56 - compatible 57 - reg 58 - clock-names 59 - clocks 60 - "#address-cells" 61 - "#size-cells" 62 - ranges 63 64patternProperties: 65 "spi@[0-9a-f]+$": 66 type: object 67 description: GENI serial engine based SPI controller. SPI in master mode 68 supports up to 50MHz, up to four chip selects, programmable 69 data path from 4 bits to 32 bits and numerous protocol 70 variants. 71 $ref: /schemas/spi/qcom,spi-geni-qcom.yaml# 72 73 "i2c@[0-9a-f]+$": 74 type: object 75 description: GENI serial engine based I2C controller. 76 $ref: /schemas/i2c/qcom,i2c-geni-qcom.yaml# 77 78 "serial@[0-9a-f]+$": 79 type: object 80 description: GENI Serial Engine based UART Controller. 81 $ref: /schemas/serial/qcom,serial-geni-qcom.yaml# 82 83allOf: 84 - if: 85 properties: 86 compatible: 87 contains: 88 const: qcom,geni-se-i2c-master-hub 89 then: 90 properties: 91 clock-names: 92 items: 93 - const: s-ahb 94 95 clocks: 96 items: 97 - description: Slave AHB Clock 98 99 iommus: false 100 101 patternProperties: 102 "spi@[0-9a-f]+$": false 103 "serial@[0-9a-f]+$": false 104 else: 105 properties: 106 clock-names: 107 items: 108 - const: m-ahb 109 - const: s-ahb 110 111 clocks: 112 items: 113 - description: Master AHB Clock 114 - description: Slave AHB Clock 115 116additionalProperties: false 117 118examples: 119 - | 120 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 121 #include <dt-bindings/interrupt-controller/arm-gic.h> 122 123 soc { 124 #address-cells = <2>; 125 #size-cells = <2>; 126 127 geniqup@8c0000 { 128 compatible = "qcom,geni-se-qup"; 129 reg = <0 0x008c0000 0 0x6000>; 130 clock-names = "m-ahb", "s-ahb"; 131 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 132 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 133 #address-cells = <2>; 134 #size-cells = <2>; 135 ranges; 136 137 i2c0: i2c@a94000 { 138 compatible = "qcom,geni-i2c"; 139 reg = <0 0xa94000 0 0x4000>; 140 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 141 clock-names = "se"; 142 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 143 pinctrl-names = "default", "sleep"; 144 pinctrl-0 = <&qup_1_i2c_5_active>; 145 pinctrl-1 = <&qup_1_i2c_5_sleep>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 }; 149 150 uart0: serial@a88000 { 151 compatible = "qcom,geni-uart"; 152 reg = <0 0xa88000 0 0x7000>; 153 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 154 clock-names = "se"; 155 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 156 pinctrl-names = "default", "sleep"; 157 pinctrl-0 = <&qup_1_uart_3_active>; 158 pinctrl-1 = <&qup_1_uart_3_sleep>; 159 }; 160 }; 161 }; 162 163... 164