1*d5b0e70fSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*d5b0e70fSEmmanuel Vadot# Copyright (C) 2022, Intel Corporation 3*d5b0e70fSEmmanuel Vadot%YAML 1.2 4*d5b0e70fSEmmanuel Vadot--- 5*d5b0e70fSEmmanuel Vadot$id: "http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#" 6*d5b0e70fSEmmanuel Vadot$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7*d5b0e70fSEmmanuel Vadot 8*d5b0e70fSEmmanuel Vadottitle: Intel HPS Copy Engine 9*d5b0e70fSEmmanuel Vadot 10*d5b0e70fSEmmanuel Vadotmaintainers: 11*d5b0e70fSEmmanuel Vadot - Matthew Gerlach <matthew.gerlach@linux.intel.com> 12*d5b0e70fSEmmanuel Vadot 13*d5b0e70fSEmmanuel Vadotdescription: | 14*d5b0e70fSEmmanuel Vadot The Intel Hard Processor System (HPS) Copy Engine is an IP block used to copy 15*d5b0e70fSEmmanuel Vadot a bootable image from host memory to HPS DDR. Additionally, there is a 16*d5b0e70fSEmmanuel Vadot register the HPS can use to indicate the state of booting the copied image as 17*d5b0e70fSEmmanuel Vadot well as a keep-a-live indication to the host. 18*d5b0e70fSEmmanuel Vadot 19*d5b0e70fSEmmanuel Vadotproperties: 20*d5b0e70fSEmmanuel Vadot compatible: 21*d5b0e70fSEmmanuel Vadot const: intel,hps-copy-engine 22*d5b0e70fSEmmanuel Vadot 23*d5b0e70fSEmmanuel Vadot '#dma-cells': 24*d5b0e70fSEmmanuel Vadot const: 1 25*d5b0e70fSEmmanuel Vadot 26*d5b0e70fSEmmanuel Vadot reg: 27*d5b0e70fSEmmanuel Vadot maxItems: 1 28*d5b0e70fSEmmanuel Vadot 29*d5b0e70fSEmmanuel Vadotrequired: 30*d5b0e70fSEmmanuel Vadot - compatible 31*d5b0e70fSEmmanuel Vadot - reg 32*d5b0e70fSEmmanuel Vadot 33*d5b0e70fSEmmanuel VadotadditionalProperties: false 34*d5b0e70fSEmmanuel Vadot 35*d5b0e70fSEmmanuel Vadotexamples: 36*d5b0e70fSEmmanuel Vadot - | 37*d5b0e70fSEmmanuel Vadot bus@80000000 { 38*d5b0e70fSEmmanuel Vadot compatible = "simple-bus"; 39*d5b0e70fSEmmanuel Vadot reg = <0x80000000 0x60000000>, 40*d5b0e70fSEmmanuel Vadot <0xf9000000 0x00100000>; 41*d5b0e70fSEmmanuel Vadot reg-names = "axi_h2f", "axi_h2f_lw"; 42*d5b0e70fSEmmanuel Vadot #address-cells = <2>; 43*d5b0e70fSEmmanuel Vadot #size-cells = <1>; 44*d5b0e70fSEmmanuel Vadot ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>; 45*d5b0e70fSEmmanuel Vadot 46*d5b0e70fSEmmanuel Vadot dma-controller@0 { 47*d5b0e70fSEmmanuel Vadot compatible = "intel,hps-copy-engine"; 48*d5b0e70fSEmmanuel Vadot reg = <0x00000000 0x00000000 0x00001000>; 49*d5b0e70fSEmmanuel Vadot #dma-cells = <1>; 50*d5b0e70fSEmmanuel Vadot }; 51*d5b0e70fSEmmanuel Vadot }; 52