1* Run Control and Power Management 2------------------------------------------- 3The RCPM performs all device-level tasks associated with device run control 4and power management. 5 6Required properites: 7 - reg : Offset and length of the register set of the RCPM block. 8 - #fsl,rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the 9 fsl,rcpm-wakeup property. 10 - compatible : Must contain a chip-specific RCPM block compatible string 11 and (if applicable) may contain a chassis-version RCPM compatible 12 string. Chip-specific strings are of the form "fsl,<chip>-rcpm", 13 such as: 14 * "fsl,p2041-rcpm" 15 * "fsl,p5020-rcpm" 16 * "fsl,t4240-rcpm" 17 18 Chassis-version strings are of the form "fsl,qoriq-rcpm-<version>", 19 such as: 20 * "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm 21 * "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm 22 * "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm 23 * "fsl,qoriq-rcpm-2.1+": for chassis 2.1+ rcpm 24 25All references to "1.0" and "2.0" refer to the QorIQ chassis version to 26which the chip complies. 27Chassis Version Example Chips 28--------------- ------------------------------- 291.0 p4080, p5020, p5040, p2041, p3041 302.0 t4240, b4860, b4420 312.1 t1040, 322.1+ ls1021a, ls1012a, ls1043a, ls1046a 33 34Optional properties: 35 - little-endian : RCPM register block is Little Endian. Without it RCPM 36 will be Big Endian (default case). 37 38Example: 39The RCPM node for T4240: 40 rcpm: global-utilities@e2000 { 41 compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0"; 42 reg = <0xe2000 0x1000>; 43 #fsl,rcpm-wakeup-cells = <2>; 44 }; 45 46* Freescale RCPM Wakeup Source Device Tree Bindings 47------------------------------------------- 48Required fsl,rcpm-wakeup property should be added to a device node if the device 49can be used as a wakeup source. 50 51 - fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR 52 register cells. The number of IPPDEXPCR register cells is defined in 53 "#fsl,rcpm-wakeup-cells" in the rcpm node. The first register cell is 54 the bit mask that should be set in IPPDEXPCR0, and the second register 55 cell is for IPPDEXPCR1, and so on. 56 57 Note: IPPDEXPCR(IP Powerdown Exception Control Register) provides a 58 mechanism for keeping certain blocks awake during STANDBY and MEM, in 59 order to use them as wake-up sources. 60 61Example: 62 lpuart0: serial@2950000 { 63 compatible = "fsl,ls1021a-lpuart"; 64 reg = <0x0 0x2950000 0x0 0x1000>; 65 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 66 clocks = <&sysclk>; 67 clock-names = "ipg"; 68 fsl,rcpm-wakeup = <&rcpm 0x0 0x40000000>; 69 }; 70