1Every GPIO controller node must have #gpio-cells property defined, 2this information will be used to translate gpio-specifiers. 3 4On CPM1 devices, all ports are using slightly different register layouts. 5Ports A, C and D are 16bit ports and Ports B and E are 32bit ports. 6 7On CPM2 devices, all ports are 32bit ports and use a common register layout. 8 9Required properties: 10- compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b", 11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d", 12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank" 13- #gpio-cells : Should be two. The first cell is the pin number and the 14 second cell is used to specify optional parameters (currently unused). 15- gpio-controller : Marks the port as GPIO controller. 16Optional properties: 17- fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C 18 on CPM1), this item tells which ports have an associated interrupt (ports are 19 listed in the same order as in PCINT register) 20- interrupts : This property provides the list of interrupt for each GPIO having 21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as 22 many interrupts as number of ones in the mask property. The first interrupt in 23 the list corresponds to the most significant bit of the mask. 24 25Example of four SOC GPIO banks defined as gpio-controller nodes: 26 27 CPM1_PIO_A: gpio-controller@950 { 28 #gpio-cells = <2>; 29 compatible = "fsl,cpm1-pario-bank-a"; 30 reg = <0x950 0x10>; 31 gpio-controller; 32 }; 33 34 CPM1_PIO_B: gpio-controller@ab8 { 35 #gpio-cells = <2>; 36 compatible = "fsl,cpm1-pario-bank-b"; 37 reg = <0xab8 0x10>; 38 gpio-controller; 39 }; 40 41 CPM1_PIO_C: gpio-controller@960 { 42 #gpio-cells = <2>; 43 compatible = "fsl,cpm1-pario-bank-c"; 44 reg = <0x960 0x10>; 45 fsl,cpm1-gpio-irq-mask = <0x0fff>; 46 interrupts = <1 2 6 9 10 11 14 15 23 24 26 31>; 47 interrupt-parent = <&CPM_PIC>; 48 gpio-controller; 49 }; 50 51 CPM1_PIO_E: gpio-controller@ac8 { 52 #gpio-cells = <2>; 53 compatible = "fsl,cpm1-pario-bank-e"; 54 reg = <0xac8 0x18>; 55 gpio-controller; 56 }; 57