xref: /freebsd/sys/contrib/device-tree/Bindings/serial/renesas,hscif.yaml (revision 5def4c47d4bd90b209b9b4a4ba9faec15846d8fd) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/serial/renesas,hscif.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Renesas High Speed Serial Communication Interface with FIFO (HSCIF)
8
9maintainers:
10  - Geert Uytterhoeven <geert+renesas@glider.be>
11
12allOf:
13  - $ref: serial.yaml#
14
15properties:
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - renesas,hscif-r8a7778      # R-Car M1
21              - renesas,hscif-r8a7779      # R-Car H1
22          - const: renesas,rcar-gen1-hscif # R-Car Gen1
23          - const: renesas,hscif           # generic HSCIF compatible UART
24
25      - items:
26          - enum:
27              - renesas,hscif-r8a7742      # RZ/G1H
28              - renesas,hscif-r8a7743      # RZ/G1M
29              - renesas,hscif-r8a7744      # RZ/G1N
30              - renesas,hscif-r8a7745      # RZ/G1E
31              - renesas,hscif-r8a77470     # RZ/G1C
32              - renesas,hscif-r8a7790      # R-Car H2
33              - renesas,hscif-r8a7791      # R-Car M2-W
34              - renesas,hscif-r8a7792      # R-Car V2H
35              - renesas,hscif-r8a7793      # R-Car M2-N
36              - renesas,hscif-r8a7794      # R-Car E2
37          - const: renesas,rcar-gen2-hscif # R-Car Gen2 and RZ/G1
38          - const: renesas,hscif           # generic HSCIF compatible UART
39
40      - items:
41          - enum:
42              - renesas,hscif-r8a774a1     # RZ/G2M
43              - renesas,hscif-r8a774b1     # RZ/G2N
44              - renesas,hscif-r8a774c0     # RZ/G2E
45              - renesas,hscif-r8a774e1     # RZ/G2H
46              - renesas,hscif-r8a7795      # R-Car H3
47              - renesas,hscif-r8a7796      # R-Car M3-W
48              - renesas,hscif-r8a77961     # R-Car M3-W+
49              - renesas,hscif-r8a77965     # R-Car M3-N
50              - renesas,hscif-r8a77970     # R-Car V3M
51              - renesas,hscif-r8a77980     # R-Car V3H
52              - renesas,hscif-r8a77990     # R-Car E3
53              - renesas,hscif-r8a77995     # R-Car D3
54              - renesas,hscif-r8a779a0     # R-Car V3U
55          - const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G2
56          - const: renesas,hscif           # generic HSCIF compatible UART
57
58  reg:
59    maxItems: 1
60
61  interrupts:
62    maxItems: 1
63
64  clocks:
65    minItems: 1
66    maxItems: 4
67
68  clock-names:
69    minItems: 1
70    maxItems: 4
71    items:
72      enum:
73        - fck # UART functional clock
74        - hsck # optional external clock input
75        - brg_int # optional internal clock source for BRG frequency divider
76        - scif_clk # optional external clock source for BRG frequency divider
77
78  power-domains:
79    maxItems: 1
80
81  resets:
82    maxItems: 1
83
84  dmas:
85    minItems: 2
86    maxItems: 4
87    description:
88      Must contain a list of pairs of references to DMA specifiers, one for
89      transmission, and one for reception.
90
91  dma-names:
92    minItems: 2
93    maxItems: 4
94    items:
95      enum:
96        - tx
97        - rx
98
99required:
100  - compatible
101  - reg
102  - interrupts
103  - clocks
104  - clock-names
105  - power-domains
106
107unevaluatedProperties: false
108
109if:
110  properties:
111    compatible:
112      contains:
113        enum:
114          - renesas,rcar-gen2-hscif
115          - renesas,rcar-gen3-hscif
116then:
117  required:
118    - resets
119
120examples:
121  - |
122    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
123    #include <dt-bindings/interrupt-controller/arm-gic.h>
124    #include <dt-bindings/power/r8a7795-sysc.h>
125    aliases {
126            serial1 = &hscif1;
127    };
128
129    hscif1: serial@e6550000 {
130            compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif",
131                         "renesas,hscif";
132            reg = <0xe6550000 96>;
133            interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
134            clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>,
135                     <&scif_clk>;
136            clock-names = "fck", "brg_int", "scif_clk";
137            dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>;
138            dma-names = "tx", "rx", "tx", "rx";
139            power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
140            resets = <&cpg 519>;
141            uart-has-rtscts;
142    };
143