xref: /freebsd/sys/contrib/device-tree/Bindings/serial/fsl-imx-uart.yaml (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
8
9maintainers:
10  - Fabio Estevam <festevam@gmail.com>
11
12allOf:
13  - $ref: serial.yaml#
14  - $ref: rs485.yaml#
15
16properties:
17  compatible:
18    oneOf:
19      - const: fsl,imx1-uart
20      - const: fsl,imx21-uart
21      - items:
22          - enum:
23              - fsl,imx25-uart
24              - fsl,imx27-uart
25              - fsl,imx31-uart
26              - fsl,imx35-uart
27              - fsl,imx50-uart
28              - fsl,imx51-uart
29              - fsl,imx53-uart
30              - fsl,imx6q-uart
31          - const: fsl,imx21-uart
32      - items:
33          - enum:
34              - fsl,imx6sl-uart
35              - fsl,imx6sll-uart
36              - fsl,imx6sx-uart
37          - const: fsl,imx6q-uart
38          - const: fsl,imx21-uart
39      - items:
40          - enum:
41              - fsl,imx6ul-uart
42              - fsl,imx7d-uart
43              - fsl,imx8mm-uart
44              - fsl,imx8mn-uart
45              - fsl,imx8mp-uart
46              - fsl,imx8mq-uart
47          - const: fsl,imx6q-uart
48
49  reg:
50    maxItems: 1
51
52  clocks:
53    maxItems: 2
54
55  clock-names:
56    items:
57      - const: ipg
58      - const: per
59
60  dmas:
61    items:
62      - description: DMA controller phandle and request line for RX
63      - description: DMA controller phandle and request line for TX
64
65  dma-names:
66    items:
67      - const: rx
68      - const: tx
69
70  interrupts:
71    maxItems: 1
72
73  fsl,dte-mode:
74    $ref: /schemas/types.yaml#/definitions/flag
75    description: |
76      Indicate the uart works in DTE mode. The uart works in DCE mode by default.
77
78  fsl,inverted-tx:
79    $ref: /schemas/types.yaml#/definitions/flag
80    description: |
81      Indicate that the hardware attached to the peripheral inverts the signal
82      transmitted, and that the peripheral should invert its output using the
83      INVT registers.
84
85  fsl,inverted-rx:
86    $ref: /schemas/types.yaml#/definitions/flag
87    description: |
88      Indicate that the hardware attached to the peripheral inverts the signal
89      received, and that the peripheral should invert its input using the
90      INVR registers.
91
92  fsl,dma-info:
93    $ref: /schemas/types.yaml#/definitions/uint32-array
94    minItems: 2
95    maxItems: 2
96    description: |
97      First cell contains the size of DMA buffer chunks, second cell contains
98      the amount of chunks used for the device. Multiplying both numbers is
99      the total size of memory used for receiving data.
100      When not being configured the system will use default settings, which
101      are sensible for most use cases. If you need low latency processing on
102      slow connections this needs to be configured appropriately.
103
104required:
105  - compatible
106  - reg
107  - clocks
108  - clock-names
109  - interrupts
110
111unevaluatedProperties: false
112
113examples:
114  - |
115    #include <dt-bindings/clock/imx5-clock.h>
116
117    aliases {
118        serial0 = &uart1;
119    };
120
121    uart1: serial@73fbc000 {
122        compatible = "fsl,imx51-uart", "fsl,imx21-uart";
123        reg = <0x73fbc000 0x4000>;
124        interrupts = <31>;
125        clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
126                 <&clks IMX5_CLK_UART1_PER_GATE>;
127        clock-names = "ipg", "per";
128        dmas = <&sdma 18 4 1>, <&sdma 19 4 2>;
129        dma-names = "rx", "tx";
130        uart-has-rtscts;
131        fsl,dte-mode;
132    };
133