xref: /freebsd/sys/contrib/device-tree/Bindings/serial/cdns,uart.yaml (revision c7046f76c2c027b00c0e6ba57cfd28f1a78f5e23) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/cdns,uart.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence UART Controller Device Tree Bindings
8
9maintainers:
10  - Michal Simek <michal.simek@xilinx.com>
11
12allOf:
13  - $ref: /schemas/serial.yaml#
14
15properties:
16  compatible:
17    oneOf:
18      - description: UART controller for Zynq-7xxx SoC
19        items:
20          - const: xlnx,xuartps
21          - const: cdns,uart-r1p8
22      - description: UART controller for Zynq Ultrascale+ MPSoC
23        items:
24          - const: xlnx,zynqmp-uart
25          - const: cdns,uart-r1p12
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    maxItems: 1
32
33  clocks:
34    maxItems: 2
35
36  clock-names:
37    items:
38      - const: uart_clk
39      - const: pclk
40
41  cts-override:
42    description: |
43      Override the CTS modem status signal. This signal will
44      always be reported as active instead of being obtained
45      from the modem status register. Define this if your serial
46      port does not use this pin.
47    type: boolean
48
49required:
50  - compatible
51  - reg
52  - interrupts
53  - clocks
54  - clock-names
55
56unevaluatedProperties: false
57
58examples:
59  - |
60    uart0: serial@e0000000 {
61      compatible = "xlnx,xuartps", "cdns,uart-r1p8";
62      clocks = <&clkc 23>, <&clkc 40>;
63      clock-names = "uart_clk", "pclk";
64      reg = <0xE0000000 0x1000>;
65      interrupts = <0 27 4>;
66    };
67