xref: /freebsd/sys/contrib/device-tree/Bindings/serial/8250.yaml (revision dc318a4ffabcbfa23bb56a33403aad36e6de30af) 
1# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/8250.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: UART (Universal Asynchronous Receiver/Transmitter) bindings
8
9maintainers:
10  - devicetree@vger.kernel.org
11
12allOf:
13  - $ref: /schemas/serial.yaml#
14  - if:
15      required:
16        - aspeed,sirq-polarity-sense
17    then:
18      properties:
19        compatible:
20          const: aspeed,ast2500-vuart
21  - if:
22      properties:
23        compatible:
24          const: mrvl,mmp-uart
25    then:
26      properties:
27        reg-shift:
28          const: 2
29      required:
30        - reg-shift
31  - if:
32      not:
33        properties:
34          compatible:
35            items:
36              - enum:
37                  - ns8250
38                  - ns16450
39                  - ns16550
40                  - ns16550a
41    then:
42      anyOf:
43        - required: [ clock-frequency ]
44        - required: [ clocks ]
45
46properties:
47  compatible:
48    oneOf:
49      - const: ns8250
50      - const: ns16450
51      - const: ns16550
52      - const: ns16550a
53      - const: ns16850
54      - const: aspeed,ast2400-vuart
55      - const: aspeed,ast2500-vuart
56      - const: intel,xscale-uart
57      - const: mrvl,pxa-uart
58      - const: nuvoton,npcm750-uart
59      - const: nvidia,tegra20-uart
60      - const: nxp,lpc3220-uart
61      - items:
62          - enum:
63              - altr,16550-FIFO32
64              - altr,16550-FIFO64
65              - altr,16550-FIFO128
66              - fsl,16550-FIFO64
67              - fsl,ns16550
68              - andestech,uart16550
69              - nxp,lpc1850-uart
70              - opencores,uart16550-rtlsvn105
71              - ti,da830-uart
72          - const: ns16550a
73      - items:
74          - enum:
75              - ns16750
76              - cavium,octeon-3860-uart
77              - xlnx,xps-uart16550-2.00.b
78              - ralink,rt2880-uart
79          - enum:
80              - ns16550 # Deprecated, unless the FIFO really is broken
81              - ns16550a
82      - items:
83          - enum:
84              - ralink,mt7620a-uart
85              - ralink,rt3052-uart
86              - ralink,rt3883-uart
87          - const: ralink,rt2880-uart
88          - enum:
89              - ns16550 # Deprecated, unless the FIFO really is broken
90              - ns16550a
91      - items:
92          - enum:
93              - mediatek,mt7622-btif
94              - mediatek,mt7623-btif
95          - const: mediatek,mtk-btif
96      - items:
97          - enum:
98              - mediatek,mt7622-btif
99              - mediatek,mt7623-btif
100          - const: mediatek,mtk-btif
101      - items:
102          - const: mrvl,mmp-uart
103          - const: intel,xscale-uart
104      - items:
105          - enum:
106              - nvidia,tegra30-uart
107              - nvidia,tegra114-uart
108              - nvidia,tegra124-uart
109              - nvidia,tegra186-uart
110              - nvidia,tegra194-uart
111              - nvidia,tegra210-uart
112          - const: nvidia,tegra20-uart
113
114  reg:
115    maxItems: 1
116
117  interrupts:
118    maxItems: 1
119
120  clock-frequency: true
121
122  clocks:
123    maxItems: 1
124
125  resets:
126    maxItems: 1
127
128  current-speed:
129    $ref: /schemas/types.yaml#definitions/uint32
130    description: The current active speed of the UART.
131
132  reg-offset:
133    description: |
134      Offset to apply to the mapbase from the start of the registers.
135
136  reg-shift:
137    description: Quantity to shift the register offsets by.
138
139  reg-io-width:
140    description: |
141      The size (in bytes) of the IO accesses that should be performed on the
142      device. There are some systems that require 32-bit accesses to the
143      UART (e.g. TI davinci).
144
145  used-by-rtas:
146    type: boolean
147    description: |
148      Set to indicate that the port is in use by the OpenFirmware RTAS and
149      should not be registered.
150
151  no-loopback-test:
152    type: boolean
153    description: |
154      Set to indicate that the port does not implement loopback test mode.
155
156  fifo-size:
157    $ref: /schemas/types.yaml#definitions/uint32
158    description: The fifo size of the UART.
159
160  auto-flow-control:
161    type: boolean
162    description: |
163      One way to enable automatic flow control support. The driver is
164      allowed to detect support for the capability even without this
165      property.
166
167  tx-threshold:
168    $ref: /schemas/types.yaml#definitions/uint32
169    description: |
170      Specify the TX FIFO low water indication for parts with programmable
171      TX FIFO thresholds.
172
173  overrun-throttle-ms:
174    description: |
175      How long to pause uart rx when input overrun is encountered.
176
177  rts-gpios: true
178  cts-gpios: true
179  dtr-gpios: true
180  dsr-gpios: true
181  rng-gpios: true
182  dcd-gpios: true
183
184  aspeed,sirq-polarity-sense:
185    $ref: /schemas/types.yaml#/definitions/phandle-array
186    description: |
187      Phandle to aspeed,ast2500-scu compatible syscon alongside register
188      offset and bit number to identify how the SIRQ polarity should be
189      configured. One possible data source is the LPC/eSPI mode bit. Only
190      applicable to aspeed,ast2500-vuart.
191
192required:
193  - reg
194  - interrupts
195
196unevaluatedProperties: false
197
198examples:
199  - |
200    serial@80230000 {
201        compatible = "ns8250";
202        reg = <0x80230000 0x100>;
203        interrupts = <10>;
204        reg-shift = <2>;
205        clock-frequency = <48000000>;
206    };
207  - |
208    #include <dt-bindings/gpio/gpio.h>
209    serial@49042000 {
210        compatible = "andestech,uart16550", "ns16550a";
211        reg = <0x49042000 0x400>;
212        interrupts = <80>;
213        clock-frequency = <48000000>;
214        cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
215        rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
216        dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
217        dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
218        dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
219        rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
220    };
221  - |
222    #include <dt-bindings/clock/aspeed-clock.h>
223    serial@1e787000 {
224        compatible = "aspeed,ast2500-vuart";
225        reg = <0x1e787000 0x40>;
226        reg-shift = <2>;
227        interrupts = <8>;
228        clocks = <&syscon ASPEED_CLK_APB>;
229        no-loopback-test;
230        aspeed,sirq-polarity-sense = <&syscon 0x70 25>;
231    };
232
233...
234