1SiFive L2 Cache Controller 2-------------------------- 3The SiFive Level 2 Cache Controller is used to provide access to fast copies 4of memory for masters in a Core Complex. The Level 2 Cache Controller also 5acts as directory-based coherency manager. 6All the properties in ePAPR/DeviceTree specification applies for this platform 7 8Required Properties: 9-------------------- 10- compatible: Should be "sifive,fu540-c000-ccache" and "cache" 11 12- cache-block-size: Specifies the block size in bytes of the cache. 13 Should be 64 14 15- cache-level: Should be set to 2 for a level 2 cache 16 17- cache-sets: Specifies the number of associativity sets of the cache. 18 Should be 1024 19 20- cache-size: Specifies the size in bytes of the cache. Should be 2097152 21 22- cache-unified: Specifies the cache is a unified cache 23 24- interrupts: Must contain 3 entries (DirError, DataError and DataFail signals) 25 26- reg: Physical base address and size of L2 cache controller registers map 27 28Optional Properties: 29-------------------- 30- next-level-cache: phandle to the next level cache if present. 31 32- memory-region: reference to the reserved-memory for the L2 Loosely Integrated 33 Memory region. The reserved memory node should be defined as per the bindings 34 in reserved-memory.txt 35 36 37Example: 38 39 cache-controller@2010000 { 40 compatible = "sifive,fu540-c000-ccache", "cache"; 41 cache-block-size = <64>; 42 cache-level = <2>; 43 cache-sets = <1024>; 44 cache-size = <2097152>; 45 cache-unified; 46 interrupt-parent = <&plic0>; 47 interrupts = <1 2 3>; 48 reg = <0x0 0x2010000 0x0 0x1000>; 49 next-level-cache = <&L25 &L40 &L36>; 50 memory-region = <&l2_lim>; 51 }; 52