xref: /freebsd/sys/contrib/device-tree/Bindings/riscv/sifive,ccache0.yaml (revision f81cdf24ba5436367377f7c8e8f51f6df2a75ca7) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive Composable Cache Controller
9
10maintainers:
11  - Paul Walmsley <paul.walmsley@sifive.com>
12
13description:
14  The SiFive Composable Cache Controller is used to provide access to fast copies
15  of memory for masters in a Core Complex. The Composable Cache Controller also
16  acts as directory-based coherency manager.
17  All the properties in ePAPR/DeviceTree specification applies for this platform.
18
19select:
20  properties:
21    compatible:
22      contains:
23        enum:
24          - sifive,ccache0
25          - sifive,fu540-c000-ccache
26          - sifive,fu740-c000-ccache
27
28  required:
29    - compatible
30
31properties:
32  compatible:
33    oneOf:
34      - items:
35          - enum:
36              - sifive,ccache0
37              - sifive,fu540-c000-ccache
38              - sifive,fu740-c000-ccache
39          - const: cache
40      - items:
41          - const: starfive,jh7110-ccache
42          - const: sifive,ccache0
43          - const: cache
44      - items:
45          - const: microchip,mpfs-ccache
46          - const: sifive,fu540-c000-ccache
47          - const: cache
48
49  cache-block-size:
50    const: 64
51
52  cache-level:
53    enum: [2, 3]
54
55  cache-sets:
56    enum: [1024, 2048]
57
58  cache-size:
59    const: 2097152
60
61  cache-unified: true
62
63  interrupts:
64    minItems: 3
65    items:
66      - description: DirError interrupt
67      - description: DataError interrupt
68      - description: DataFail interrupt
69      - description: DirFail interrupt
70
71  reg:
72    maxItems: 1
73
74  next-level-cache: true
75
76  memory-region:
77    maxItems: 1
78    description: |
79      The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
80      The reserved memory node should be defined as per the bindings in reserved-memory.txt.
81
82allOf:
83  - $ref: /schemas/cache-controller.yaml#
84
85  - if:
86      properties:
87        compatible:
88          contains:
89            enum:
90              - sifive,fu740-c000-ccache
91              - starfive,jh7110-ccache
92              - microchip,mpfs-ccache
93
94    then:
95      properties:
96        interrupts:
97          description: |
98            Must contain entries for DirError, DataError, DataFail, DirFail signals.
99          minItems: 4
100
101    else:
102      properties:
103        interrupts:
104          description: |
105            Must contain entries for DirError, DataError and DataFail signals.
106          maxItems: 3
107
108  - if:
109      properties:
110        compatible:
111          contains:
112            enum:
113              - sifive,fu740-c000-ccache
114              - starfive,jh7110-ccache
115
116    then:
117      properties:
118        cache-sets:
119          const: 2048
120
121    else:
122      properties:
123        cache-sets:
124          const: 1024
125
126  - if:
127      properties:
128        compatible:
129          contains:
130            const: sifive,ccache0
131
132    then:
133      properties:
134        cache-level:
135          enum: [2, 3]
136
137    else:
138      properties:
139        cache-level:
140          const: 2
141
142additionalProperties: false
143
144required:
145  - compatible
146  - cache-block-size
147  - cache-level
148  - cache-sets
149  - cache-size
150  - cache-unified
151  - interrupts
152  - reg
153
154examples:
155  - |
156    cache-controller@2010000 {
157        compatible = "sifive,fu540-c000-ccache", "cache";
158        cache-block-size = <64>;
159        cache-level = <2>;
160        cache-sets = <1024>;
161        cache-size = <2097152>;
162        cache-unified;
163        reg = <0x2010000 0x1000>;
164        interrupt-parent = <&plic0>;
165        interrupts = <1>,
166                     <2>,
167                     <3>;
168        next-level-cache = <&L25>;
169        memory-region = <&l2_lim>;
170    };
171