1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V bindings for 'cpus' DT nodes 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 13description: | 14 This document uses some terminology common to the RISC-V community 15 that is not widely used, the definitions of which are listed here: 16 17 hart: A hardware execution context, which contains all the state 18 mandated by the RISC-V ISA: a PC and some registers. This 19 terminology is designed to disambiguate software's view of execution 20 contexts from any particular microarchitectural implementation 21 strategy. For example, an Intel laptop containing one socket with 22 two cores, each of which has two hyperthreads, could be described as 23 having four harts. 24 25properties: 26 compatible: 27 oneOf: 28 - items: 29 - enum: 30 - sifive,rocket0 31 - sifive,bullet0 32 - sifive,e5 33 - sifive,e7 34 - sifive,e71 35 - sifive,u74-mc 36 - sifive,u54 37 - sifive,u74 38 - sifive,u5 39 - sifive,u7 40 - canaan,k210 41 - const: riscv 42 - items: 43 - enum: 44 - sifive,e51 45 - sifive,u54-mc 46 - const: sifive,rocket0 47 - const: riscv 48 - const: riscv # Simulator only 49 description: 50 Identifies that the hart uses the RISC-V instruction set 51 and identifies the type of the hart. 52 53 mmu-type: 54 description: 55 Identifies the MMU address translation mode used on this 56 hart. These values originate from the RISC-V Privileged 57 Specification document, available from 58 https://riscv.org/specifications/ 59 $ref: "/schemas/types.yaml#/definitions/string" 60 enum: 61 - riscv,sv32 62 - riscv,sv39 63 - riscv,sv48 64 - riscv,none 65 66 riscv,cbom-block-size: 67 $ref: /schemas/types.yaml#/definitions/uint32 68 description: 69 The blocksize in bytes for the Zicbom cache operations. 70 71 riscv,isa: 72 description: 73 Identifies the specific RISC-V instruction set architecture 74 supported by the hart. These are documented in the RISC-V 75 User-Level ISA document, available from 76 https://riscv.org/specifications/ 77 78 While the isa strings in ISA specification are case 79 insensitive, letters in the riscv,isa string must be all 80 lowercase to simplify parsing. 81 $ref: "/schemas/types.yaml#/definitions/string" 82 enum: 83 - rv64imac 84 - rv64imafdc 85 86 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here 87 timebase-frequency: false 88 89 interrupt-controller: 90 type: object 91 description: Describes the CPU's local interrupt controller 92 93 properties: 94 '#interrupt-cells': 95 const: 1 96 97 compatible: 98 const: riscv,cpu-intc 99 100 interrupt-controller: true 101 102 required: 103 - '#interrupt-cells' 104 - compatible 105 - interrupt-controller 106 107 cpu-idle-states: 108 $ref: '/schemas/types.yaml#/definitions/phandle-array' 109 items: 110 maxItems: 1 111 description: | 112 List of phandles to idle state nodes supported 113 by this hart (see ./idle-states.yaml). 114 115required: 116 - riscv,isa 117 - interrupt-controller 118 119additionalProperties: true 120 121examples: 122 - | 123 // Example 1: SiFive Freedom U540G Development Kit 124 cpus { 125 #address-cells = <1>; 126 #size-cells = <0>; 127 timebase-frequency = <1000000>; 128 cpu@0 { 129 clock-frequency = <0>; 130 compatible = "sifive,rocket0", "riscv"; 131 device_type = "cpu"; 132 i-cache-block-size = <64>; 133 i-cache-sets = <128>; 134 i-cache-size = <16384>; 135 reg = <0>; 136 riscv,isa = "rv64imac"; 137 cpu_intc0: interrupt-controller { 138 #interrupt-cells = <1>; 139 compatible = "riscv,cpu-intc"; 140 interrupt-controller; 141 }; 142 }; 143 cpu@1 { 144 clock-frequency = <0>; 145 compatible = "sifive,rocket0", "riscv"; 146 d-cache-block-size = <64>; 147 d-cache-sets = <64>; 148 d-cache-size = <32768>; 149 d-tlb-sets = <1>; 150 d-tlb-size = <32>; 151 device_type = "cpu"; 152 i-cache-block-size = <64>; 153 i-cache-sets = <64>; 154 i-cache-size = <32768>; 155 i-tlb-sets = <1>; 156 i-tlb-size = <32>; 157 mmu-type = "riscv,sv39"; 158 reg = <1>; 159 riscv,isa = "rv64imafdc"; 160 tlb-split; 161 cpu_intc1: interrupt-controller { 162 #interrupt-cells = <1>; 163 compatible = "riscv,cpu-intc"; 164 interrupt-controller; 165 }; 166 }; 167 }; 168 169 - | 170 // Example 2: Spike ISA Simulator with 1 Hart 171 cpus { 172 #address-cells = <1>; 173 #size-cells = <0>; 174 cpu@0 { 175 device_type = "cpu"; 176 reg = <0>; 177 compatible = "riscv"; 178 riscv,isa = "rv64imafdc"; 179 mmu-type = "riscv,sv48"; 180 interrupt-controller { 181 #interrupt-cells = <1>; 182 interrupt-controller; 183 compatible = "riscv,cpu-intc"; 184 }; 185 }; 186 }; 187... 188