xref: /freebsd/sys/contrib/device-tree/Bindings/riscv/cpus.yaml (revision 6be3386466ab79a84b48429ae66244f21526d3df) 
1# SPDX-License-Identifier: (GPL-2.0 OR MIT)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/riscv/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: RISC-V bindings for 'cpus' DT nodes
8
9maintainers:
10  - Paul Walmsley <paul.walmsley@sifive.com>
11  - Palmer Dabbelt <palmer@sifive.com>
12
13description: |
14  This document uses some terminology common to the RISC-V community
15  that is not widely used, the definitions of which are listed here:
16
17  hart: A hardware execution context, which contains all the state
18  mandated by the RISC-V ISA: a PC and some registers.  This
19  terminology is designed to disambiguate software's view of execution
20  contexts from any particular microarchitectural implementation
21  strategy.  For example, an Intel laptop containing one socket with
22  two cores, each of which has two hyperthreads, could be described as
23  having four harts.
24
25properties:
26  compatible:
27    oneOf:
28      - items:
29          - enum:
30              - sifive,rocket0
31              - sifive,e5
32              - sifive,e51
33              - sifive,u54-mc
34              - sifive,u54
35              - sifive,u5
36          - const: riscv
37      - const: riscv    # Simulator only
38    description:
39      Identifies that the hart uses the RISC-V instruction set
40      and identifies the type of the hart.
41
42  mmu-type:
43    description:
44      Identifies the MMU address translation mode used on this
45      hart.  These values originate from the RISC-V Privileged
46      Specification document, available from
47      https://riscv.org/specifications/
48    $ref: "/schemas/types.yaml#/definitions/string"
49    enum:
50      - riscv,sv32
51      - riscv,sv39
52      - riscv,sv48
53
54  riscv,isa:
55    description:
56      Identifies the specific RISC-V instruction set architecture
57      supported by the hart.  These are documented in the RISC-V
58      User-Level ISA document, available from
59      https://riscv.org/specifications/
60
61      While the isa strings in ISA specification are case
62      insensitive, letters in the riscv,isa string must be all
63      lowercase to simplify parsing.
64    $ref: "/schemas/types.yaml#/definitions/string"
65    enum:
66      - rv64imac
67      - rv64imafdc
68
69  # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
70  timebase-frequency: false
71
72  interrupt-controller:
73    type: object
74    description: Describes the CPU's local interrupt controller
75
76    properties:
77      '#interrupt-cells':
78        const: 1
79
80      compatible:
81        const: riscv,cpu-intc
82
83      interrupt-controller: true
84
85    required:
86      - '#interrupt-cells'
87      - compatible
88      - interrupt-controller
89
90required:
91  - riscv,isa
92  - interrupt-controller
93
94additionalProperties: true
95
96examples:
97  - |
98    // Example 1: SiFive Freedom U540G Development Kit
99    cpus {
100        #address-cells = <1>;
101        #size-cells = <0>;
102        timebase-frequency = <1000000>;
103        cpu@0 {
104                clock-frequency = <0>;
105                compatible = "sifive,rocket0", "riscv";
106                device_type = "cpu";
107                i-cache-block-size = <64>;
108                i-cache-sets = <128>;
109                i-cache-size = <16384>;
110                reg = <0>;
111                riscv,isa = "rv64imac";
112                cpu_intc0: interrupt-controller {
113                        #interrupt-cells = <1>;
114                        compatible = "riscv,cpu-intc";
115                        interrupt-controller;
116                };
117        };
118        cpu@1 {
119                clock-frequency = <0>;
120                compatible = "sifive,rocket0", "riscv";
121                d-cache-block-size = <64>;
122                d-cache-sets = <64>;
123                d-cache-size = <32768>;
124                d-tlb-sets = <1>;
125                d-tlb-size = <32>;
126                device_type = "cpu";
127                i-cache-block-size = <64>;
128                i-cache-sets = <64>;
129                i-cache-size = <32768>;
130                i-tlb-sets = <1>;
131                i-tlb-size = <32>;
132                mmu-type = "riscv,sv39";
133                reg = <1>;
134                riscv,isa = "rv64imafdc";
135                tlb-split;
136                cpu_intc1: interrupt-controller {
137                        #interrupt-cells = <1>;
138                        compatible = "riscv,cpu-intc";
139                        interrupt-controller;
140                };
141        };
142    };
143
144  - |
145    // Example 2: Spike ISA Simulator with 1 Hart
146    cpus {
147        #address-cells = <1>;
148        #size-cells = <0>;
149        cpu@0 {
150                device_type = "cpu";
151                reg = <0>;
152                compatible = "riscv";
153                riscv,isa = "rv64imafdc";
154                mmu-type = "riscv,sv48";
155                interrupt-controller {
156                        #interrupt-cells = <1>;
157                        interrupt-controller;
158                        compatible = "riscv,cpu-intc";
159                };
160        };
161    };
162...
163