1# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Xilinx R5F processor subsystem 8 9maintainers: 10 - Ben Levinsky <ben.levinsky@amd.com> 11 - Tanmay Shah <tanmay.shah@amd.com> 12 13description: | 14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for 15 real-time processing based on the Cortex-R5F processor core from ARM. 16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a 17 floating-point unit that implements the Arm VFPv3 instruction set. 18 19properties: 20 compatible: 21 const: xlnx,zynqmp-r5fss 22 23 xlnx,cluster-mode: 24 $ref: /schemas/types.yaml#/definitions/uint32 25 enum: [0, 1, 2] 26 description: | 27 The RPU MPCore can operate in split mode (Dual-processor performance), Safety 28 lock-step mode(Both RPU cores execute the same code in lock-step, 29 clock-for-clock) or Single CPU mode (RPU core 0 is held in reset while 30 core 1 runs normally). The processor does not support dynamic configuration. 31 Switching between modes is only permitted immediately after a processor reset. 32 If set to 1 then lockstep mode and if 0 then split mode. 33 If set to 2 then single CPU mode. When not defined, default will be lockstep mode. 34 In summary, 35 0: split mode 36 1: lockstep mode (default) 37 2: single cpu mode 38 39patternProperties: 40 "^r5f-[a-f0-9]+$": 41 type: object 42 description: | 43 The RPU is located in the Low Power Domain of the Processor Subsystem. 44 Each processor includes separate L1 instruction and data caches and 45 tightly coupled memories (TCM). System memory is cacheable, but the TCM 46 memory space is non-cacheable. 47 48 Each RPU contains one 64KB memory and two 32KB memories that 49 are accessed via the TCM A and B port interfaces, for a total of 128KB 50 per processor. In lock-step mode, the processor has access to 256KB of 51 TCM memory. 52 53 properties: 54 compatible: 55 const: xlnx,zynqmp-r5f 56 57 power-domains: 58 maxItems: 1 59 60 mboxes: 61 minItems: 1 62 items: 63 - description: mailbox channel to send data to RPU 64 - description: mailbox channel to receive data from RPU 65 66 mbox-names: 67 minItems: 1 68 items: 69 - const: tx 70 - const: rx 71 72 sram: 73 $ref: /schemas/types.yaml#/definitions/phandle-array 74 minItems: 1 75 maxItems: 8 76 items: 77 maxItems: 1 78 description: | 79 phandles to one or more reserved on-chip SRAM regions. Other than TCM, 80 the RPU can execute instructions and access data from the OCM memory, 81 the main DDR memory, and other system memories. 82 83 The regions should be defined as child nodes of the respective SRAM 84 node, and should be defined as per the generic bindings in 85 Documentation/devicetree/bindings/sram/sram.yaml 86 87 memory-region: 88 description: | 89 List of phandles to the reserved memory regions associated with the 90 remoteproc device. This is variable and describes the memories shared with 91 the remote processor (e.g. remoteproc firmware and carveouts, rpmsg 92 vrings, ...). This reserved memory region will be allocated in DDR memory. 93 minItems: 1 94 maxItems: 8 95 items: 96 - description: region used for RPU firmware image section 97 - description: vdev buffer 98 - description: vring0 99 - description: vring1 100 additionalItems: true 101 102 required: 103 - compatible 104 - power-domains 105 106 unevaluatedProperties: false 107 108required: 109 - compatible 110 111additionalProperties: false 112 113examples: 114 - | 115 remoteproc { 116 compatible = "xlnx,zynqmp-r5fss"; 117 xlnx,cluster-mode = <1>; 118 119 r5f-0 { 120 compatible = "xlnx,zynqmp-r5f"; 121 power-domains = <&zynqmp_firmware 0x7>; 122 memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; 123 mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; 124 mbox-names = "tx", "rx"; 125 }; 126 127 r5f-1 { 128 compatible = "xlnx,zynqmp-r5f"; 129 power-domains = <&zynqmp_firmware 0x8>; 130 memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; 131 mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; 132 mbox-names = "tx", "rx"; 133 }; 134 }; 135... 136