1# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: OMAP4+ Remoteproc Devices 8 9maintainers: 10 - Suman Anna <s-anna@ti.com> 11 12description: 13 The OMAP family of SoCs usually have one or more slave processor sub-systems 14 that are used to offload some of the processor-intensive tasks, or to manage 15 other hardware accelerators, for achieving various system level goals. 16 17 The processor cores in the sub-system are usually behind an IOMMU, and may 18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2 19 caches, an Interrupt Controller, a Cache Controller etc. 20 21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor 22 sub-system. The DSP processor sub-system can contain any of the TI's C64x, 23 C66x or C67x family of DSP cores as the main execution unit. The IPU processor 24 sub-system usually contains either a Dual-Core Cortex-M3 or Dual-Core 25 Cortex-M4 processors. 26 27 Each remote processor sub-system is represented as a single DT node. Each node 28 has a number of required or optional properties that enable the OS running on 29 the host processor (MPU) to perform the device management of the remote 30 processor and to communicate with the remote processor. The various properties 31 can be classified as constant or variable. The constant properties are 32 dictated by the SoC and does not change from one board to another having the 33 same SoC. Examples of constant properties include 'iommus', 'reg'. The 34 variable properties are dictated by the system integration aspects such as 35 memory on the board, or configuration used within the corresponding firmware 36 image. Examples of variable properties include 'mboxes', 'memory-region', 37 'timers', 'watchdog-timers' etc. 38 39properties: 40 compatible: 41 enum: 42 - ti,omap4-dsp 43 - ti,omap5-dsp 44 - ti,dra7-dsp 45 - ti,omap4-ipu 46 - ti,omap5-ipu 47 - ti,dra7-ipu 48 49 iommus: 50 minItems: 1 51 maxItems: 2 52 description: | 53 phandles to OMAP IOMMU nodes, that need to be programmed 54 for this remote processor to access any external RAM memory or 55 other peripheral device address spaces. This property usually 56 has only a single phandle. Multiple phandles are used only in 57 cases where the sub-system has different ports for different 58 sub-modules within the processor sub-system (eg: DRA7 DSPs), 59 and need the same programming in both the MMUs. 60 61 mboxes: 62 minItems: 1 63 maxItems: 2 64 description: | 65 OMAP Mailbox specifier denoting the sub-mailbox, to be used for 66 communication with the remote processor. The specifier format is 67 as per the bindings, 68 Documentation/devicetree/bindings/mailbox/omap-mailbox.txt 69 This property should match with the sub-mailbox node used in 70 the firmware image. 71 72 clocks: 73 maxItems: 1 74 description: | 75 Main functional clock for the remote processor 76 77 resets: 78 minItems: 1 79 maxItems: 2 80 description: | 81 Reset handles for the remote processor 82 83 firmware-name: 84 description: | 85 Default name of the firmware to load to the remote processor. 86 87# Optional properties: 88# -------------------- 89# Some of these properties are mandatory on some SoCs, and some are optional 90# depending on the configuration of the firmware image to be executed on the 91# remote processor. The conditions are mentioned for each property. 92# 93# The following are the optional properties: 94 95 memory-region: 96 maxItems: 1 97 description: | 98 phandle to the reserved memory node to be associated 99 with the remoteproc device. The reserved memory node 100 can be a CMA memory node, and should be defined as 101 per the bindings, 102 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt 103 104 reg: 105 description: | 106 Address space for any remoteproc memories present on 107 the SoC. Should contain an entry for each value in 108 'reg-names'. These are mandatory for all DSP and IPU 109 processors that have them (OMAP4/OMAP5 DSPs do not have 110 any RAMs) 111 112 reg-names: 113 description: | 114 Required names for each of the address spaces defined in 115 the 'reg' property. Expects the names from the following 116 list, in the specified order, each representing the corresponding 117 internal RAM memory region. 118 minItems: 1 119 maxItems: 3 120 items: 121 - const: l2ram 122 - const: l1pram 123 - const: l1dram 124 125 ti,bootreg: 126 $ref: /schemas/types.yaml#/definitions/phandle-array 127 description: | 128 Should be a triple of the phandle to the System Control 129 Configuration region that contains the boot address 130 register, the register offset of the boot address 131 register within the System Control module, and the bit 132 shift within the register. This property is required for 133 all the DSP instances on OMAP4, OMAP5 and DRA7xx SoCs. 134 135 ti,autosuspend-delay-ms: 136 description: | 137 Custom autosuspend delay for the remoteproc in milliseconds. 138 Recommended values is preferable to be in the order of couple 139 of seconds. A negative value can also be used to disable the 140 autosuspend behavior. 141 142 ti,timers: 143 $ref: /schemas/types.yaml#/definitions/phandle-array 144 description: | 145 One or more phandles to OMAP DMTimer nodes, that serve 146 as System/Tick timers for the OS running on the remote 147 processors. This will usually be a single timer if the 148 processor sub-system is running in SMP mode, or one per 149 core in the processor sub-system. This can also be used 150 to reserve specific timers to be dedicated to the 151 remote processors. 152 153 This property is mandatory on remote processors requiring 154 external tick wakeup, and to support Power Management 155 features. The timers to be used should match with the 156 timers used in the firmware image. 157 158 ti,watchdog-timers: 159 $ref: /schemas/types.yaml#/definitions/phandle-array 160 description: | 161 One or more phandles to OMAP DMTimer nodes, used to 162 serve as Watchdog timers for the processor cores. This 163 will usually be one per executing processor core, even 164 if the processor sub-system is running a SMP OS. 165 166 The timers to be used should match with the watchdog 167 timers used in the firmware image. 168 169if: 170 properties: 171 compatible: 172 enum: 173 - ti,dra7-dsp 174then: 175 properties: 176 reg: 177 minItems: 3 178 maxItems: 3 179 required: 180 - reg 181 - reg-names 182 - ti,bootreg 183 184else: 185 if: 186 properties: 187 compatible: 188 enum: 189 - ti,omap4-ipu 190 - ti,omap5-ipu 191 - ti,dra7-ipu 192 then: 193 properties: 194 reg: 195 minItems: 1 196 maxItems: 1 197 ti,bootreg: false 198 required: 199 - reg 200 - reg-names 201 202 else: 203 properties: 204 reg: false 205 required: 206 - ti,bootreg 207 208required: 209 - compatible 210 - iommus 211 - mboxes 212 - clocks 213 - resets 214 - firmware-name 215 216additionalProperties: false 217 218examples: 219 - | 220 221 //Example 1: OMAP4 DSP 222 223 /* DSP Reserved Memory node */ 224 #include <dt-bindings/clock/omap4.h> 225 reserved-memory { 226 #address-cells = <1>; 227 #size-cells = <1>; 228 229 dsp_memory_region: dsp-memory@98000000 { 230 compatible = "shared-dma-pool"; 231 reg = <0x98000000 0x800000>; 232 reusable; 233 }; 234 }; 235 236 /* DSP node */ 237 ocp { 238 dsp: dsp { 239 compatible = "ti,omap4-dsp"; 240 ti,bootreg = <&scm_conf 0x304 0>; 241 iommus = <&mmu_dsp>; 242 mboxes = <&mailbox &mbox_dsp>; 243 memory-region = <&dsp_memory_region>; 244 ti,timers = <&timer5>; 245 ti,watchdog-timers = <&timer6>; 246 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>; 247 resets = <&prm_tesla 0>, <&prm_tesla 1>; 248 firmware-name = "omap4-dsp-fw.xe64T"; 249 }; 250 }; 251 252 - |+ 253 254 //Example 2: OMAP5 IPU 255 256 /* IPU Reserved Memory node */ 257 #include <dt-bindings/clock/omap5.h> 258 reserved-memory { 259 #address-cells = <2>; 260 #size-cells = <2>; 261 262 ipu_memory_region: ipu-memory@95800000 { 263 compatible = "shared-dma-pool"; 264 reg = <0 0x95800000 0 0x3800000>; 265 reusable; 266 }; 267 }; 268 269 /* IPU node */ 270 ocp { 271 #address-cells = <1>; 272 #size-cells = <1>; 273 274 ipu: ipu@55020000 { 275 compatible = "ti,omap5-ipu"; 276 reg = <0x55020000 0x10000>; 277 reg-names = "l2ram"; 278 iommus = <&mmu_ipu>; 279 mboxes = <&mailbox &mbox_ipu>; 280 memory-region = <&ipu_memory_region>; 281 ti,timers = <&timer3>, <&timer4>; 282 ti,watchdog-timers = <&timer9>, <&timer11>; 283 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; 284 resets = <&prm_core 2>; 285 firmware-name = "omap5-ipu-fw.xem4"; 286 }; 287 }; 288 289 - |+ 290 291 //Example 3: DRA7xx/AM57xx DSP 292 293 /* DSP1 Reserved Memory node */ 294 #include <dt-bindings/clock/dra7.h> 295 reserved-memory { 296 #address-cells = <2>; 297 #size-cells = <2>; 298 299 dsp1_memory_region: dsp1-memory@99000000 { 300 compatible = "shared-dma-pool"; 301 reg = <0x0 0x99000000 0x0 0x4000000>; 302 reusable; 303 }; 304 }; 305 306 /* DSP1 node */ 307 ocp { 308 #address-cells = <1>; 309 #size-cells = <1>; 310 311 dsp1: dsp@40800000 { 312 compatible = "ti,dra7-dsp"; 313 reg = <0x40800000 0x48000>, 314 <0x40e00000 0x8000>, 315 <0x40f00000 0x8000>; 316 reg-names = "l2ram", "l1pram", "l1dram"; 317 ti,bootreg = <&scm_conf 0x55c 0>; 318 iommus = <&mmu0_dsp1>, <&mmu1_dsp1>; 319 mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; 320 memory-region = <&dsp1_memory_region>; 321 ti,timers = <&timer5>; 322 ti,watchdog-timers = <&timer10>; 323 resets = <&prm_dsp1 0>; 324 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; 325 firmware-name = "dra7-dsp1-fw.xe66"; 326 }; 327 }; 328