1# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: TI K3 R5F processor subsystems 8 9maintainers: 10 - Suman Anna <s-anna@ti.com> 11 12description: | 13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F 14 processor subsystems/clusters (R5FSS). The dual core cluster can be used 15 either in a LockStep mode providing safety/fault tolerance features or in a 16 Split mode providing two individual compute cores for doubling the compute 17 capacity. These are used together with other processors present on the SoC 18 to achieve various system level goals. 19 20 Each Dual-Core R5F sub-system is represented as a single DTS node 21 representing the cluster, with a pair of child DT nodes representing 22 the individual R5F cores. Each node has a number of required or optional 23 properties that enable the OS running on the host processor to perform 24 the device management of the remote processor and to communicate with the 25 remote processor. 26 27properties: 28 $nodename: 29 pattern: "^r5fss(@.*)?" 30 31 compatible: 32 enum: 33 - ti,am654-r5fss 34 - ti,j721e-r5fss 35 36 power-domains: 37 description: | 38 Should contain a phandle to a PM domain provider node and an args 39 specifier containing the R5FSS device id value. 40 maxItems: 1 41 42 "#address-cells": 43 const: 1 44 45 "#size-cells": 46 const: 1 47 48 ranges: 49 description: | 50 Standard ranges definition providing address translations for 51 local R5F TCM address spaces to bus addresses. 52 53# Optional properties: 54# -------------------- 55 56 ti,cluster-mode: 57 $ref: /schemas/types.yaml#/definitions/uint32 58 enum: [0, 1] 59 description: | 60 Configuration Mode for the Dual R5F cores within the R5F cluster. 61 Should be either a value of 1 (LockStep mode) or 0 (Split mode), 62 default is LockStep mode if omitted. 63 64# R5F Processor Child Nodes: 65# ========================== 66 67patternProperties: 68 "^r5f@[a-f0-9]+$": 69 type: object 70 description: | 71 The R5F Sub-System device node should define two R5F child nodes, each 72 node representing a TI instantiation of the Arm Cortex R5F core. There 73 are some specific integration differences for the IP like the usage of 74 a Region Address Translator (RAT) for translating the larger SoC bus 75 addresses into a 32-bit address space for the processor. 76 77 Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM) 78 internal memories split between two banks - TCMA and TCMB (further 79 interleaved into two banks TCMB0 and TCMB1). These memories (also called 80 ATCM and BTCM) provide read/write performance on par with the core's L1 81 caches. Each of the TCMs can be enabled or disabled independently and 82 either of them can be configured to appear at that R5F's address 0x0. 83 84 The cores do not use an MMU, but has a Region Address Translater 85 (RAT) module that is accessible only from the R5Fs for providing 86 translations between 32-bit CPU addresses into larger system bus 87 addresses. Cache and memory access settings are provided through a 88 Memory Protection Unit (MPU), programmable only from the R5Fs. 89 90 allOf: 91 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# 92 93 properties: 94 compatible: 95 enum: 96 - ti,am654-r5f 97 - ti,j721e-r5f 98 99 reg: 100 items: 101 - description: Address and Size of the ATCM internal memory region 102 - description: Address and Size of the BTCM internal memory region 103 104 reg-names: 105 items: 106 - const: atcm 107 - const: btcm 108 109 resets: 110 description: | 111 Should contain the phandle to the reset controller node managing the 112 local resets for this device, and a reset specifier. 113 maxItems: 1 114 115 firmware-name: 116 description: | 117 Should contain the name of the default firmware image 118 file located on the firmware search path 119 120# The following properties are mandatory for R5F Core0 in both LockStep and Split 121# modes, and are mandatory for R5F Core1 _only_ in Split mode. They are unused for 122# R5F Core1 in LockStep mode: 123 124 mboxes: 125 description: | 126 OMAP Mailbox specifier denoting the sub-mailbox, to be used for 127 communication with the remote processor. This property should match 128 with the sub-mailbox node used in the firmware image. 129 maxItems: 1 130 131 memory-region: 132 description: | 133 phandle to the reserved memory nodes to be associated with the 134 remoteproc device. There should be at least two reserved memory nodes 135 defined. The reserved memory nodes should be carveout nodes, and 136 should be defined with a "no-map" property as per the bindings in 137 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt 138 minItems: 2 139 maxItems: 8 140 items: 141 - description: region used for dynamic DMA allocations like vrings and 142 vring buffers 143 - description: region reserved for firmware image sections 144 additionalItems: true 145 146 147# Optional properties: 148# -------------------- 149# The following properties are optional properties for each of the R5F cores: 150 151 ti,atcm-enable: 152 $ref: /schemas/types.yaml#/definitions/uint32 153 enum: [0, 1] 154 description: | 155 R5F core configuration mode dictating if ATCM should be enabled. The 156 R5F address of ATCM is dictated by ti,loczrama property. Should be 157 either a value of 1 (enabled) or 0 (disabled), default is disabled 158 if omitted. Recommended to enable it for maximizing TCMs. 159 160 ti,btcm-enable: 161 $ref: /schemas/types.yaml#/definitions/uint32 162 enum: [0, 1] 163 description: | 164 R5F core configuration mode dictating if BTCM should be enabled. The 165 R5F address of BTCM is dictated by ti,loczrama property. Should be 166 either a value of 1 (enabled) or 0 (disabled), default is enabled if 167 omitted. 168 169 ti,loczrama: 170 $ref: /schemas/types.yaml#/definitions/uint32 171 enum: [0, 1] 172 description: | 173 R5F core configuration mode dictating which TCM should appear at 174 address 0 (from core's view). Should be either a value of 1 (ATCM 175 at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted. 176 177 sram: 178 $ref: /schemas/types.yaml#/definitions/phandle-array 179 minItems: 1 180 maxItems: 4 181 description: | 182 phandles to one or more reserved on-chip SRAM regions. The regions 183 should be defined as child nodes of the respective SRAM node, and 184 should be defined as per the generic bindings in, 185 Documentation/devicetree/bindings/sram/sram.yaml 186 187 required: 188 - compatible 189 - reg 190 - reg-names 191 - ti,sci 192 - ti,sci-dev-id 193 - ti,sci-proc-ids 194 - resets 195 - firmware-name 196 197 unevaluatedProperties: false 198 199required: 200 - compatible 201 - power-domains 202 - "#address-cells" 203 - "#size-cells" 204 - ranges 205 206additionalProperties: false 207 208examples: 209 - | 210 / { 211 model = "Texas Instruments K3 AM654 SoC"; 212 compatible = "ti,am654-evm", "ti,am654"; 213 #address-cells = <2>; 214 #size-cells = <2>; 215 216 bus@100000 { 217 compatible = "simple-bus"; 218 #address-cells = <2>; 219 #size-cells = <2>; 220 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 221 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, 222 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, 223 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; 224 225 bus@28380000 { 226 compatible = "simple-bus"; 227 #address-cells = <2>; 228 #size-cells = <2>; 229 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS */ 230 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ 231 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ 232 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */ 233 234 /* AM65x MCU R5FSS node */ 235 mcu_r5fss0: r5fss@41000000 { 236 compatible = "ti,am654-r5fss"; 237 power-domains = <&k3_pds 129>; 238 ti,cluster-mode = <1>; 239 #address-cells = <1>; 240 #size-cells = <1>; 241 ranges = <0x41000000 0x00 0x41000000 0x20000>, 242 <0x41400000 0x00 0x41400000 0x20000>; 243 244 mcu_r5f0: r5f@41000000 { 245 compatible = "ti,am654-r5f"; 246 reg = <0x41000000 0x00008000>, 247 <0x41010000 0x00008000>; 248 reg-names = "atcm", "btcm"; 249 ti,sci = <&dmsc>; 250 ti,sci-dev-id = <159>; 251 ti,sci-proc-ids = <0x01 0xFF>; 252 resets = <&k3_reset 159 1>; 253 firmware-name = "am65x-mcu-r5f0_0-fw"; 254 ti,atcm-enable = <1>; 255 ti,btcm-enable = <1>; 256 ti,loczrama = <1>; 257 mboxes = <&mailbox0 &mbox_mcu_r5fss0_core0>; 258 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 259 <&mcu_r5fss0_core0_memory_region>; 260 sram = <&mcu_r5fss0_core0_sram>; 261 }; 262 263 mcu_r5f1: r5f@41400000 { 264 compatible = "ti,am654-r5f"; 265 reg = <0x41400000 0x00008000>, 266 <0x41410000 0x00008000>; 267 reg-names = "atcm", "btcm"; 268 ti,sci = <&dmsc>; 269 ti,sci-dev-id = <245>; 270 ti,sci-proc-ids = <0x02 0xFF>; 271 resets = <&k3_reset 245 1>; 272 firmware-name = "am65x-mcu-r5f0_1-fw"; 273 ti,atcm-enable = <1>; 274 ti,btcm-enable = <1>; 275 ti,loczrama = <1>; 276 mboxes = <&mailbox1 &mbox_mcu_r5fss0_core1>; 277 }; 278 }; 279 }; 280 }; 281 }; 282