1# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: TI K3 R5F processor subsystems 8 9maintainers: 10 - Suman Anna <s-anna@ti.com> 11 12description: | 13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F 14 processor subsystems/clusters (R5FSS). The dual core cluster can be used 15 either in a LockStep mode providing safety/fault tolerance features or in a 16 Split mode providing two individual compute cores for doubling the compute 17 capacity on most SoCs. These are used together with other processors present 18 on the SoC to achieve various system level goals. 19 20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode 21 called "Single-CPU" mode, where only Core0 is used, but with ability to use 22 Core1's TCMs as well. 23 24 Each Dual-Core R5F sub-system is represented as a single DTS node 25 representing the cluster, with a pair of child DT nodes representing 26 the individual R5F cores. Each node has a number of required or optional 27 properties that enable the OS running on the host processor to perform 28 the device management of the remote processor and to communicate with the 29 remote processor. 30 31properties: 32 $nodename: 33 pattern: "^r5fss(@.*)?" 34 35 compatible: 36 enum: 37 - ti,am654-r5fss 38 - ti,j721e-r5fss 39 - ti,j7200-r5fss 40 - ti,am64-r5fss 41 - ti,j721s2-r5fss 42 43 power-domains: 44 description: | 45 Should contain a phandle to a PM domain provider node and an args 46 specifier containing the R5FSS device id value. 47 maxItems: 1 48 49 "#address-cells": 50 const: 1 51 52 "#size-cells": 53 const: 1 54 55 ranges: 56 description: | 57 Standard ranges definition providing address translations for 58 local R5F TCM address spaces to bus addresses. 59 60# Optional properties: 61# -------------------- 62 63 ti,cluster-mode: 64 $ref: /schemas/types.yaml#/definitions/uint32 65 description: | 66 Configuration Mode for the Dual R5F cores within the R5F cluster. 67 Should be either a value of 1 (LockStep mode) or 0 (Split mode) on 68 most SoCs (AM65x, J721E, J7200, J721s2), default is LockStep mode if 69 omitted; and should be either a value of 0 (Split mode) or 2 70 (Single-CPU mode) on AM64x SoCs, default is Split mode if omitted. 71 72# R5F Processor Child Nodes: 73# ========================== 74 75patternProperties: 76 "^r5f@[a-f0-9]+$": 77 type: object 78 description: | 79 The R5F Sub-System device node should define two R5F child nodes, each 80 node representing a TI instantiation of the Arm Cortex R5F core. There 81 are some specific integration differences for the IP like the usage of 82 a Region Address Translator (RAT) for translating the larger SoC bus 83 addresses into a 32-bit address space for the processor. 84 85 Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM) 86 internal memories split between two banks - TCMA and TCMB (further 87 interleaved into two banks TCMB0 and TCMB1). These memories (also called 88 ATCM and BTCM) provide read/write performance on par with the core's L1 89 caches. Each of the TCMs can be enabled or disabled independently and 90 either of them can be configured to appear at that R5F's address 0x0. 91 92 The cores do not use an MMU, but has a Region Address Translater 93 (RAT) module that is accessible only from the R5Fs for providing 94 translations between 32-bit CPU addresses into larger system bus 95 addresses. Cache and memory access settings are provided through a 96 Memory Protection Unit (MPU), programmable only from the R5Fs. 97 98 $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# 99 100 properties: 101 compatible: 102 enum: 103 - ti,am654-r5f 104 - ti,j721e-r5f 105 - ti,j7200-r5f 106 - ti,am64-r5f 107 - ti,j721s2-r5f 108 109 reg: 110 items: 111 - description: Address and Size of the ATCM internal memory region 112 - description: Address and Size of the BTCM internal memory region 113 114 reg-names: 115 items: 116 - const: atcm 117 - const: btcm 118 119 resets: 120 description: | 121 Should contain the phandle to the reset controller node managing the 122 local resets for this device, and a reset specifier. 123 maxItems: 1 124 125 firmware-name: 126 description: | 127 Should contain the name of the default firmware image 128 file located on the firmware search path 129 130# The following properties are mandatory for R5F Core0 in both LockStep and Split 131# modes, and are mandatory for R5F Core1 _only_ in Split mode. They are unused for 132# R5F Core1 in LockStep mode: 133 134 mboxes: 135 description: | 136 OMAP Mailbox specifier denoting the sub-mailbox, to be used for 137 communication with the remote processor. This property should match 138 with the sub-mailbox node used in the firmware image. 139 maxItems: 1 140 141 memory-region: 142 description: | 143 phandle to the reserved memory nodes to be associated with the 144 remoteproc device. There should be at least two reserved memory nodes 145 defined. The reserved memory nodes should be carveout nodes, and 146 should be defined with a "no-map" property as per the bindings in 147 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt 148 minItems: 2 149 maxItems: 8 150 items: 151 - description: region used for dynamic DMA allocations like vrings and 152 vring buffers 153 - description: region reserved for firmware image sections 154 additionalItems: true 155 156 157# Optional properties: 158# -------------------- 159# The following properties are optional properties for each of the R5F cores: 160 161 ti,atcm-enable: 162 $ref: /schemas/types.yaml#/definitions/uint32 163 enum: [0, 1] 164 description: | 165 R5F core configuration mode dictating if ATCM should be enabled. The 166 R5F address of ATCM is dictated by ti,loczrama property. Should be 167 either a value of 1 (enabled) or 0 (disabled), default is disabled 168 if omitted. Recommended to enable it for maximizing TCMs. 169 170 ti,btcm-enable: 171 $ref: /schemas/types.yaml#/definitions/uint32 172 enum: [0, 1] 173 description: | 174 R5F core configuration mode dictating if BTCM should be enabled. The 175 R5F address of BTCM is dictated by ti,loczrama property. Should be 176 either a value of 1 (enabled) or 0 (disabled), default is enabled if 177 omitted. 178 179 ti,loczrama: 180 $ref: /schemas/types.yaml#/definitions/uint32 181 enum: [0, 1] 182 description: | 183 R5F core configuration mode dictating which TCM should appear at 184 address 0 (from core's view). Should be either a value of 1 (ATCM 185 at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted. 186 187 sram: 188 $ref: /schemas/types.yaml#/definitions/phandle-array 189 minItems: 1 190 maxItems: 4 191 items: 192 maxItems: 1 193 description: | 194 phandles to one or more reserved on-chip SRAM regions. The regions 195 should be defined as child nodes of the respective SRAM node, and 196 should be defined as per the generic bindings in, 197 Documentation/devicetree/bindings/sram/sram.yaml 198 199 required: 200 - compatible 201 - reg 202 - reg-names 203 - ti,sci 204 - ti,sci-dev-id 205 - ti,sci-proc-ids 206 - resets 207 - firmware-name 208 209 unevaluatedProperties: false 210 211if: 212 properties: 213 compatible: 214 enum: 215 - ti,am64-r5fss 216then: 217 properties: 218 ti,cluster-mode: 219 enum: [0, 2] 220else: 221 properties: 222 ti,cluster-mode: 223 enum: [0, 1] 224 225required: 226 - compatible 227 - power-domains 228 - "#address-cells" 229 - "#size-cells" 230 - ranges 231 232additionalProperties: false 233 234examples: 235 - | 236 soc { 237 #address-cells = <2>; 238 #size-cells = <2>; 239 240 mailbox0: mailbox-0 { 241 #mbox-cells = <1>; 242 }; 243 244 mailbox1: mailbox-1 { 245 #mbox-cells = <1>; 246 }; 247 248 bus@100000 { 249 compatible = "simple-bus"; 250 #address-cells = <2>; 251 #size-cells = <2>; 252 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 253 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, 254 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, 255 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; 256 257 bus@28380000 { 258 compatible = "simple-bus"; 259 #address-cells = <2>; 260 #size-cells = <2>; 261 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS */ 262 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ 263 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ 264 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */ 265 266 /* AM65x MCU R5FSS node */ 267 mcu_r5fss0: r5fss@41000000 { 268 compatible = "ti,am654-r5fss"; 269 power-domains = <&k3_pds 129>; 270 ti,cluster-mode = <1>; 271 #address-cells = <1>; 272 #size-cells = <1>; 273 ranges = <0x41000000 0x00 0x41000000 0x20000>, 274 <0x41400000 0x00 0x41400000 0x20000>; 275 276 mcu_r5f0: r5f@41000000 { 277 compatible = "ti,am654-r5f"; 278 reg = <0x41000000 0x00008000>, 279 <0x41010000 0x00008000>; 280 reg-names = "atcm", "btcm"; 281 ti,sci = <&dmsc>; 282 ti,sci-dev-id = <159>; 283 ti,sci-proc-ids = <0x01 0xFF>; 284 resets = <&k3_reset 159 1>; 285 firmware-name = "am65x-mcu-r5f0_0-fw"; 286 ti,atcm-enable = <1>; 287 ti,btcm-enable = <1>; 288 ti,loczrama = <1>; 289 mboxes = <&mailbox0 &mbox_mcu_r5fss0_core0>; 290 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 291 <&mcu_r5fss0_core0_memory_region>; 292 sram = <&mcu_r5fss0_core0_sram>; 293 }; 294 295 mcu_r5f1: r5f@41400000 { 296 compatible = "ti,am654-r5f"; 297 reg = <0x41400000 0x00008000>, 298 <0x41410000 0x00008000>; 299 reg-names = "atcm", "btcm"; 300 ti,sci = <&dmsc>; 301 ti,sci-dev-id = <245>; 302 ti,sci-proc-ids = <0x02 0xFF>; 303 resets = <&k3_reset 245 1>; 304 firmware-name = "am65x-mcu-r5f0_1-fw"; 305 ti,atcm-enable = <1>; 306 ti,btcm-enable = <1>; 307 ti,loczrama = <1>; 308 mboxes = <&mailbox1 &mbox_mcu_r5fss0_core1>; 309 }; 310 }; 311 }; 312 }; 313 }; 314