1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/remoteproc/qcom,sm8550-pas.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SM8550 Peripheral Authentication Service 8 9maintainers: 10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 11 12description: 13 Qualcomm SM8550 SoC Peripheral Authentication Service loads and boots firmware 14 on the Qualcomm DSP Hexagon cores. 15 16properties: 17 compatible: 18 enum: 19 - qcom,sm8550-adsp-pas 20 - qcom,sm8550-cdsp-pas 21 - qcom,sm8550-mpss-pas 22 23 reg: 24 maxItems: 1 25 26 clocks: 27 items: 28 - description: XO clock 29 30 clock-names: 31 items: 32 - const: xo 33 34 qcom,qmp: 35 $ref: /schemas/types.yaml#/definitions/phandle 36 description: Reference to the AOSS side-channel message RAM. 37 38 smd-edge: false 39 40 firmware-name: 41 $ref: /schemas/types.yaml#/definitions/string-array 42 items: 43 - description: Firmware name of the Hexagon core 44 - description: Firmware name of the Hexagon Devicetree 45 46 memory-region: 47 minItems: 2 48 items: 49 - description: Memory region for main Firmware authentication 50 - description: Memory region for Devicetree Firmware authentication 51 - description: DSM Memory region 52 53required: 54 - compatible 55 - reg 56 57allOf: 58 - $ref: /schemas/remoteproc/qcom,pas-common.yaml# 59 - if: 60 properties: 61 compatible: 62 enum: 63 - qcom,sm8550-adsp-pas 64 - qcom,sm8550-cdsp-pas 65 then: 66 properties: 67 interrupts: 68 maxItems: 5 69 interrupt-names: 70 maxItems: 5 71 memory-region: 72 maxItems: 2 73 else: 74 properties: 75 interrupts: 76 minItems: 6 77 interrupt-names: 78 minItems: 6 79 memory-region: 80 minItems: 3 81 82 - if: 83 properties: 84 compatible: 85 enum: 86 - qcom,sm8550-adsp-pas 87 then: 88 properties: 89 power-domains: 90 items: 91 - description: LCX power domain 92 - description: LMX power domain 93 power-domain-names: 94 items: 95 - const: lcx 96 - const: lmx 97 98 - if: 99 properties: 100 compatible: 101 enum: 102 - qcom,sm8550-mpss-pas 103 then: 104 properties: 105 power-domains: 106 items: 107 - description: CX power domain 108 - description: MSS power domain 109 power-domain-names: 110 items: 111 - const: cx 112 - const: mss 113 - if: 114 properties: 115 compatible: 116 enum: 117 - qcom,sm8550-cdsp-pas 118 then: 119 properties: 120 power-domains: 121 items: 122 - description: CX power domain 123 - description: MXC power domain 124 - description: NSP power domain 125 power-domain-names: 126 items: 127 - const: cx 128 - const: mxc 129 - const: nsp 130 131unevaluatedProperties: false 132 133examples: 134 - | 135 #include <dt-bindings/clock/qcom,rpmh.h> 136 #include <dt-bindings/interrupt-controller/irq.h> 137 #include <dt-bindings/mailbox/qcom-ipcc.h> 138 139 remoteproc@30000000 { 140 compatible = "qcom,sm8550-adsp-pas"; 141 reg = <0x030000000 0x100>; 142 143 clocks = <&rpmhcc RPMH_CXO_CLK>; 144 clock-names = "xo"; 145 146 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 147 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 148 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 149 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 150 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 151 interrupt-names = "wdog", "fatal", "ready", 152 "handover", "stop-ack"; 153 154 memory-region = <&adsp_mem>, <&dtb_adsp_mem>; 155 156 firmware-name = "qcom/sm8550/adsp.mbn", 157 "qcom/sm8550/adsp_dtb.mbn"; 158 159 power-domains = <&rpmhpd_sm8550_lcx>, 160 <&rpmhpd_sm8550_lmx>; 161 power-domain-names = "lcx", "lmx"; 162 163 qcom,qmp = <&aoss_qmp>; 164 qcom,smem-states = <&smp2p_adsp_out 0>; 165 qcom,smem-state-names = "stop"; 166 167 glink-edge { 168 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 169 IPCC_MPROC_SIGNAL_GLINK_QMP 170 IRQ_TYPE_EDGE_RISING>; 171 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>; 172 173 label = "lpass"; 174 qcom,remote-pid = <2>; 175 176 /* ... */ 177 }; 178 }; 179