1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-wpss-pil.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SC7280 WPSS Peripheral Image Loader 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 12description: 13 This document defines the binding for a component that loads and boots firmware 14 on the Qualcomm Technology Inc. WPSS. 15 16properties: 17 compatible: 18 enum: 19 - qcom,sc7280-wpss-pil 20 21 reg: 22 maxItems: 1 23 description: 24 The base address and size of the qdsp6ss register 25 26 interrupts: 27 items: 28 - description: Watchdog interrupt 29 - description: Fatal interrupt 30 - description: Ready interrupt 31 - description: Handover interrupt 32 - description: Stop acknowledge interrupt 33 - description: Shutdown acknowledge interrupt 34 35 interrupt-names: 36 items: 37 - const: wdog 38 - const: fatal 39 - const: ready 40 - const: handover 41 - const: stop-ack 42 - const: shutdown-ack 43 44 clocks: 45 items: 46 - description: GCC WPSS AHB BDG Master clock 47 - description: GCC WPSS AHB clock 48 - description: GCC WPSS RSCP clock 49 - description: XO clock 50 51 clock-names: 52 items: 53 - const: ahb_bdg 54 - const: ahb 55 - const: rscp 56 - const: xo 57 58 power-domains: 59 items: 60 - description: CX power domain 61 - description: MX power domain 62 63 power-domain-names: 64 items: 65 - const: cx 66 - const: mx 67 68 resets: 69 items: 70 - description: AOSS restart 71 - description: PDC SYNC 72 73 reset-names: 74 items: 75 - const: restart 76 - const: pdc_sync 77 78 memory-region: 79 $ref: /schemas/types.yaml#/definitions/phandle 80 description: Reference to the reserved-memory for the Hexagon core 81 82 firmware-name: 83 $ref: /schemas/types.yaml#/definitions/string 84 description: 85 The name of the firmware which should be loaded for this remote 86 processor. 87 88 qcom,halt-regs: 89 $ref: /schemas/types.yaml#/definitions/phandle-array 90 description: 91 Phandle reference to a syscon representing TCSR followed by the 92 three offsets within syscon for q6, modem and nc halt registers. 93 94 qcom,qmp: 95 $ref: /schemas/types.yaml#/definitions/phandle 96 description: Reference to the AOSS side-channel message RAM. 97 98 qcom,smem-states: 99 $ref: /schemas/types.yaml#/definitions/phandle-array 100 description: States used by the AP to signal the Hexagon core 101 items: 102 - description: Stop the modem 103 104 qcom,smem-state-names: 105 $ref: /schemas/types.yaml#/definitions/string 106 description: The names of the state bits used for SMP2P output 107 const: stop 108 109 glink-edge: 110 type: object 111 description: | 112 Qualcomm G-Link subnode which represents communication edge, channels 113 and devices related to the ADSP. 114 115 properties: 116 interrupts: 117 items: 118 - description: IRQ from WPSS to GLINK 119 120 mboxes: 121 items: 122 - description: Mailbox for communication between APPS and WPSS 123 124 label: 125 description: The names of the state bits used for SMP2P output 126 items: 127 - const: wpss 128 129 qcom,remote-pid: 130 $ref: /schemas/types.yaml#/definitions/uint32 131 description: ID of the shared memory used by GLINK for communication with WPSS 132 133 required: 134 - interrupts 135 - mboxes 136 - label 137 - qcom,remote-pid 138 139 additionalProperties: false 140 141required: 142 - compatible 143 - reg 144 - interrupts 145 - interrupt-names 146 - clocks 147 - clock-names 148 - power-domains 149 - power-domain-names 150 - resets 151 - reset-names 152 - qcom,halt-regs 153 - memory-region 154 - qcom,qmp 155 - qcom,smem-states 156 - qcom,smem-state-names 157 - glink-edge 158 159additionalProperties: false 160 161examples: 162 - | 163 #include <dt-bindings/interrupt-controller/arm-gic.h> 164 #include <dt-bindings/clock/qcom,gcc-sc7280.h> 165 #include <dt-bindings/clock/qcom,rpmh.h> 166 #include <dt-bindings/power/qcom-rpmpd.h> 167 #include <dt-bindings/reset/qcom,sdm845-aoss.h> 168 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 169 #include <dt-bindings/mailbox/qcom-ipcc.h> 170 remoteproc@8a00000 { 171 compatible = "qcom,sc7280-wpss-pil"; 172 reg = <0x08a00000 0x10000>; 173 174 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 175 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 176 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 177 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 178 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 179 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 180 interrupt-names = "wdog", "fatal", "ready", "handover", 181 "stop-ack", "shutdown-ack"; 182 183 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 184 <&gcc GCC_WPSS_AHB_CLK>, 185 <&gcc GCC_WPSS_RSCP_CLK>, 186 <&rpmhcc RPMH_CXO_CLK>; 187 clock-names = "ahb_bdg", "ahb", 188 "rscp", "xo"; 189 190 power-domains = <&rpmhpd SC7280_CX>, 191 <&rpmhpd SC7280_MX>; 192 power-domain-names = "cx", "mx"; 193 194 memory-region = <&wpss_mem>; 195 196 qcom,qmp = <&aoss_qmp>; 197 198 qcom,smem-states = <&wpss_smp2p_out 0>; 199 qcom,smem-state-names = "stop"; 200 201 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 202 <&pdc_reset PDC_WPSS_SYNC_RESET>; 203 reset-names = "restart", "pdc_sync"; 204 205 qcom,halt-regs = <&tcsr_mutex 0x37000>; 206 207 glink-edge { 208 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 209 IPCC_MPROC_SIGNAL_GLINK_QMP 210 IRQ_TYPE_EDGE_RISING>; 211 mboxes = <&ipcc IPCC_CLIENT_WPSS 212 IPCC_MPROC_SIGNAL_GLINK_QMP>; 213 214 label = "wpss"; 215 qcom,remote-pid = <13>; 216 }; 217 }; 218