1Socionext UniPhier Regulator Controller 2 3This describes the devicetree bindings for regulator controller implemented 4on Socionext UniPhier SoCs. 5 6USB3 Controller 7--------------- 8 9This regulator controls VBUS and belongs to USB3 glue layer. Before using 10the regulator, it is necessary to control the clocks and resets to enable 11this layer. These clocks and resets should be described in each property. 12 13Required properties: 14- compatible: Should be 15 "socionext,uniphier-pro4-usb3-regulator" - for Pro4 SoC 16 "socionext,uniphier-pro5-usb3-regulator" - for Pro5 SoC 17 "socionext,uniphier-pxs2-usb3-regulator" - for PXs2 SoC 18 "socionext,uniphier-ld20-usb3-regulator" - for LD20 SoC 19 "socionext,uniphier-pxs3-usb3-regulator" - for PXs3 SoC 20- reg: Specifies offset and length of the register set for the device. 21- clocks: A list of phandles to the clock gate for USB3 glue layer. 22 According to the clock-names, appropriate clocks are required. 23- clock-names: Should contain 24 "gio", "link" - for Pro4 and Pro5 SoCs 25 "link" - for others 26- resets: A list of phandles to the reset control for USB3 glue layer. 27 According to the reset-names, appropriate resets are required. 28- reset-names: Should contain 29 "gio", "link" - for Pro4 and Pro5 SoCs 30 "link" - for others 31 32See Documentation/devicetree/bindings/regulator/regulator.txt 33for more details about the regulator properties. 34 35Example: 36 37 usb-glue@65b00000 { 38 compatible = "socionext,uniphier-ld20-dwc3-glue", 39 "simple-mfd"; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 ranges = <0 0x65b00000 0x400>; 43 44 usb_vbus0: regulators@100 { 45 compatible = "socionext,uniphier-ld20-usb3-regulator"; 46 reg = <0x100 0x10>; 47 clock-names = "link"; 48 clocks = <&sys_clk 14>; 49 reset-names = "link"; 50 resets = <&sys_rst 14>; 51 }; 52 53 phy { 54 ... 55 phy-supply = <&usb_vbus0>; 56 }; 57 ... 58 }; 59