1SiFive PWM controller 2 3Unlike most other PWM controllers, the SiFive PWM controller currently only 4supports one period for all channels in the PWM. All PWMs need to run at 5the same period. The period also has significant restrictions on the values 6it can achieve, which the driver rounds to the nearest achievable period. 7PWM RTL that corresponds to the IP block version numbers can be found 8here: 9 10https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm 11 12Required properties: 13- compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". 14 Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive 15 PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the 16 SiFive PWM v0 IP block with no chip integration tweaks. 17 Please refer to sifive-blocks-ip-versioning.txt for details. 18- reg: physical base address and length of the controller's registers 19- clocks: Should contain a clock identifier for the PWM's parent clock. 20- #pwm-cells: Should be 3. See pwm.yaml in this directory 21 for a description of the cell format. 22- interrupts: one interrupt per PWM channel 23 24Examples: 25 26pwm: pwm@10020000 { 27 compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; 28 reg = <0x0 0x10020000 0x0 0x1000>; 29 clocks = <&tlclk>; 30 interrupt-parent = <&plic>; 31 interrupts = <42 43 44 45>; 32 #pwm-cells = <3>; 33}; 34