1MediaTek display PWM controller 2 3Required properties: 4 - compatible: should be "mediatek,<name>-disp-pwm": 5 - "mediatek,mt2701-disp-pwm": found on mt2701 SoC. 6 - "mediatek,mt6595-disp-pwm": found on mt6595 SoC. 7 - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC. 8 - "mediatek,mt8173-disp-pwm": found on mt8173 SoC. 9 - "mediatek,mt8183-disp-pwm": found on mt8183 SoC.$ 10 - reg: physical base address and length of the controller's registers. 11 - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of 12 the cell format. 13 - clocks: phandle and clock specifier of the PWM reference clock. 14 - clock-names: must contain the following: 15 - "main": clock used to generate PWM signals. 16 - "mm": sync signals from the modules of mmsys. 17 - pinctrl-names: Must contain a "default" entry. 18 - pinctrl-0: One property must exist for each entry in pinctrl-names. 19 See pinctrl/pinctrl-bindings.txt for details of the property values. 20 21Example: 22 pwm0: pwm@1401e000 { 23 compatible = "mediatek,mt8173-disp-pwm", 24 "mediatek,mt6595-disp-pwm"; 25 reg = <0 0x1401e000 0 0x1000>; 26 #pwm-cells = <2>; 27 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 28 <&mmsys CLK_MM_DISP_PWM0MM>; 29 clock-names = "main", "mm"; 30 pinctrl-names = "default"; 31 pinctrl-0 = <&disp_pwm0_pins>; 32 }; 33 34 backlight_lcd: backlight_lcd { 35 compatible = "pwm-backlight"; 36 pwms = <&pwm0 0 1000000>; 37 brightness-levels = < 38 0 16 32 48 64 80 96 112 39 128 144 160 176 192 208 224 240 40 255 41 >; 42 default-brightness-level = <9>; 43 power-supply = <&mt6397_vio18_reg>; 44 enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; 45 }; 46