1MediaTek PWM controller 2 3Required properties: 4 - compatible: should be "mediatek,<name>-pwm": 5 - "mediatek,mt2712-pwm": found on mt2712 SoC. 6 - "mediatek,mt7622-pwm": found on mt7622 SoC. 7 - "mediatek,mt7623-pwm": found on mt7623 SoC. 8 - "mediatek,mt7628-pwm": found on mt7628 SoC. 9 - "mediatek,mt7629-pwm": found on mt7629 SoC. 10 - "mediatek,mt8516-pwm": found on mt8516 SoC. 11 - reg: physical base address and length of the controller's registers. 12 - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of 13 the cell format. 14 - clocks: phandle and clock specifier of the PWM reference clock. 15 - clock-names: must contain the following, except for MT7628 which 16 has no clocks 17 - "top": the top clock generator 18 - "main": clock used by the PWM core 19 - "pwm1-8": the eight per PWM clocks for mt2712 20 - "pwm1-6": the six per PWM clocks for mt7622 21 - "pwm1-5": the five per PWM clocks for mt7623 22 - "pwm1" : the PWM1 clock for mt7629 23 - pinctrl-names: Must contain a "default" entry. 24 - pinctrl-0: One property must exist for each entry in pinctrl-names. 25 See pinctrl/pinctrl-bindings.txt for details of the property values. 26 27Optional properties: 28- assigned-clocks: Reference to the PWM clock entries. 29- assigned-clock-parents: The phandle of the parent clock of PWM clock. 30 31Example: 32 pwm0: pwm@11006000 { 33 compatible = "mediatek,mt7623-pwm"; 34 reg = <0 0x11006000 0 0x1000>; 35 #pwm-cells = <2>; 36 clocks = <&topckgen CLK_TOP_PWM_SEL>, 37 <&pericfg CLK_PERI_PWM>, 38 <&pericfg CLK_PERI_PWM1>, 39 <&pericfg CLK_PERI_PWM2>, 40 <&pericfg CLK_PERI_PWM3>, 41 <&pericfg CLK_PERI_PWM4>, 42 <&pericfg CLK_PERI_PWM5>; 43 clock-names = "top", "main", "pwm1", "pwm2", 44 "pwm3", "pwm4", "pwm5"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pwm0_pins>; 47 }; 48