1=================================================================== 2Power Architecture CPU Binding 3Copyright 2013 Freescale Semiconductor Inc. 4 5Power Architecture CPUs in Freescale SOCs are represented in device trees as 6per the definition in the Devicetree Specification. 7 8In addition to the Devicetree Specification definitions, the properties 9defined below may be present on CPU nodes. 10 11PROPERTIES 12 13 - fsl,eref-* 14 Usage: optional 15 Value type: <empty> 16 Definition: The EREF (EREF: A Programmer.s Reference Manual for 17 Freescale Power Architecture) defines the architecture for Freescale 18 Power CPUs. The EREF defines some architecture categories not defined 19 by the Power ISA. For these EREF-specific categories, the existence of 20 a property named fsl,eref-[CAT], where [CAT] is the abbreviated category 21 name with all uppercase letters converted to lowercase, indicates that 22 the category is supported by the implementation. 23 24 - fsl,portid-mapping 25 Usage: optional 26 Value type: <u32> 27 Definition: The Coherency Subdomain ID Port Mapping Registers and 28 Snoop ID Port Mapping registers, which are part of the CoreNet 29 Coherency fabric (CCF), provide a CoreNet Coherency Subdomain 30 ID/CoreNet Snoop ID to cpu mapping functions. Certain bits from 31 these registers should be set if the coresponding CPU should be 32 snooped. This property defines a bitmask which selects the bit 33 that should be set if this cpu should be snooped. 34