1* Freescale PQ3 and QorIQ based Cache SRAM 2 3Freescale's mpc85xx and some QorIQ platforms provide an 4option of configuring a part of (or full) cache memory 5as SRAM. This cache SRAM representation in the device 6tree should be done as under:- 7 8Required properties: 9 10- compatible : should be "fsl,p2020-cache-sram" 11- fsl,cache-sram-ctlr-handle : points to the L2 controller 12- reg : offset and length of the cache-sram. 13 14Example: 15 16cache-sram@fff00000 { 17 fsl,cache-sram-ctlr-handle = <&L2>; 18 reg = <0 0xfff00000 0 0x10000>; 19 compatible = "fsl,p2020-cache-sram"; 20}; 21