1*c66ec88fSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*c66ec88fSEmmanuel Vadot%YAML 1.2 3*c66ec88fSEmmanuel Vadot--- 4*c66ec88fSEmmanuel Vadot$id: http://devicetree.org/schemas/power/fsl,imx-gpc.yaml# 5*c66ec88fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel Vadottitle: Freescale i.MX General Power Controller 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadotmaintainers: 10*c66ec88fSEmmanuel Vadot - Philipp Zabel <p.zabel@pengutronix.de> 11*c66ec88fSEmmanuel Vadot 12*c66ec88fSEmmanuel Vadotdescription: | 13*c66ec88fSEmmanuel Vadot The i.MX6 General Power Control (GPC) block contains DVFS load tracking 14*c66ec88fSEmmanuel Vadot counters and Power Gating Control (PGC). 15*c66ec88fSEmmanuel Vadot 16*c66ec88fSEmmanuel Vadot The power domains are generic power domain providers as documented in 17*c66ec88fSEmmanuel Vadot Documentation/devicetree/bindings/power/power-domain.yaml. They are 18*c66ec88fSEmmanuel Vadot described as subnodes of the power gating controller 'pgc' node of the GPC. 19*c66ec88fSEmmanuel Vadot 20*c66ec88fSEmmanuel Vadot IP cores belonging to a power domain should contain a 'power-domains' 21*c66ec88fSEmmanuel Vadot property that is a phandle pointing to the power domain the device belongs 22*c66ec88fSEmmanuel Vadot to. 23*c66ec88fSEmmanuel Vadot 24*c66ec88fSEmmanuel Vadotproperties: 25*c66ec88fSEmmanuel Vadot compatible: 26*c66ec88fSEmmanuel Vadot enum: 27*c66ec88fSEmmanuel Vadot - fsl,imx6q-gpc 28*c66ec88fSEmmanuel Vadot - fsl,imx6qp-gpc 29*c66ec88fSEmmanuel Vadot - fsl,imx6sl-gpc 30*c66ec88fSEmmanuel Vadot - fsl,imx6sx-gpc 31*c66ec88fSEmmanuel Vadot 32*c66ec88fSEmmanuel Vadot reg: 33*c66ec88fSEmmanuel Vadot maxItems: 1 34*c66ec88fSEmmanuel Vadot 35*c66ec88fSEmmanuel Vadot interrupts: 36*c66ec88fSEmmanuel Vadot maxItems: 1 37*c66ec88fSEmmanuel Vadot 38*c66ec88fSEmmanuel Vadot clocks: 39*c66ec88fSEmmanuel Vadot maxItems: 1 40*c66ec88fSEmmanuel Vadot 41*c66ec88fSEmmanuel Vadot clock-names: 42*c66ec88fSEmmanuel Vadot const: ipg 43*c66ec88fSEmmanuel Vadot 44*c66ec88fSEmmanuel Vadot pgc: 45*c66ec88fSEmmanuel Vadot type: object 46*c66ec88fSEmmanuel Vadot description: list of power domains provided by this controller. 47*c66ec88fSEmmanuel Vadot 48*c66ec88fSEmmanuel Vadot patternProperties: 49*c66ec88fSEmmanuel Vadot "power-domain@[0-9]$": 50*c66ec88fSEmmanuel Vadot type: object 51*c66ec88fSEmmanuel Vadot properties: 52*c66ec88fSEmmanuel Vadot 53*c66ec88fSEmmanuel Vadot '#power-domain-cells': 54*c66ec88fSEmmanuel Vadot const: 0 55*c66ec88fSEmmanuel Vadot 56*c66ec88fSEmmanuel Vadot reg: 57*c66ec88fSEmmanuel Vadot description: | 58*c66ec88fSEmmanuel Vadot The following DOMAIN_INDEX values are valid for i.MX6Q: 59*c66ec88fSEmmanuel Vadot ARM_DOMAIN 0 60*c66ec88fSEmmanuel Vadot PU_DOMAIN 1 61*c66ec88fSEmmanuel Vadot The following additional DOMAIN_INDEX value is valid for i.MX6SL: 62*c66ec88fSEmmanuel Vadot DISPLAY_DOMAIN 2 63*c66ec88fSEmmanuel Vadot The following additional DOMAIN_INDEX value is valid for i.MX6SX: 64*c66ec88fSEmmanuel Vadot PCI_DOMAIN 3 65*c66ec88fSEmmanuel Vadot maxItems: 1 66*c66ec88fSEmmanuel Vadot 67*c66ec88fSEmmanuel Vadot clocks: 68*c66ec88fSEmmanuel Vadot description: | 69*c66ec88fSEmmanuel Vadot A number of phandles to clocks that need to be enabled during domain 70*c66ec88fSEmmanuel Vadot power-up sequencing to ensure reset propagation into devices located 71*c66ec88fSEmmanuel Vadot inside this power domain. 72*c66ec88fSEmmanuel Vadot minItems: 1 73*c66ec88fSEmmanuel Vadot maxItems: 7 74*c66ec88fSEmmanuel Vadot 75*c66ec88fSEmmanuel Vadot power-supply: true 76*c66ec88fSEmmanuel Vadot 77*c66ec88fSEmmanuel Vadot required: 78*c66ec88fSEmmanuel Vadot - '#power-domain-cells' 79*c66ec88fSEmmanuel Vadot - reg 80*c66ec88fSEmmanuel Vadot 81*c66ec88fSEmmanuel Vadotrequired: 82*c66ec88fSEmmanuel Vadot - compatible 83*c66ec88fSEmmanuel Vadot - reg 84*c66ec88fSEmmanuel Vadot - interrupts 85*c66ec88fSEmmanuel Vadot - clocks 86*c66ec88fSEmmanuel Vadot - clock-names 87*c66ec88fSEmmanuel Vadot - pgc 88*c66ec88fSEmmanuel Vadot 89*c66ec88fSEmmanuel VadotadditionalProperties: false 90*c66ec88fSEmmanuel Vadot 91*c66ec88fSEmmanuel Vadotexamples: 92*c66ec88fSEmmanuel Vadot - | 93*c66ec88fSEmmanuel Vadot #include <dt-bindings/clock/imx6qdl-clock.h> 94*c66ec88fSEmmanuel Vadot #include <dt-bindings/interrupt-controller/arm-gic.h> 95*c66ec88fSEmmanuel Vadot 96*c66ec88fSEmmanuel Vadot gpc@20dc000 { 97*c66ec88fSEmmanuel Vadot compatible = "fsl,imx6q-gpc"; 98*c66ec88fSEmmanuel Vadot reg = <0x020dc000 0x4000>; 99*c66ec88fSEmmanuel Vadot interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 100*c66ec88fSEmmanuel Vadot clocks = <&clks IMX6QDL_CLK_IPG>; 101*c66ec88fSEmmanuel Vadot clock-names = "ipg"; 102*c66ec88fSEmmanuel Vadot 103*c66ec88fSEmmanuel Vadot pgc { 104*c66ec88fSEmmanuel Vadot #address-cells = <1>; 105*c66ec88fSEmmanuel Vadot #size-cells = <0>; 106*c66ec88fSEmmanuel Vadot 107*c66ec88fSEmmanuel Vadot power-domain@0 { 108*c66ec88fSEmmanuel Vadot reg = <0>; 109*c66ec88fSEmmanuel Vadot #power-domain-cells = <0>; 110*c66ec88fSEmmanuel Vadot }; 111*c66ec88fSEmmanuel Vadot 112*c66ec88fSEmmanuel Vadot pd_pu: power-domain@1 { 113*c66ec88fSEmmanuel Vadot reg = <1>; 114*c66ec88fSEmmanuel Vadot #power-domain-cells = <0>; 115*c66ec88fSEmmanuel Vadot power-supply = <®_pu>; 116*c66ec88fSEmmanuel Vadot clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, 117*c66ec88fSEmmanuel Vadot <&clks IMX6QDL_CLK_GPU3D_SHADER>, 118*c66ec88fSEmmanuel Vadot <&clks IMX6QDL_CLK_GPU2D_CORE>, 119*c66ec88fSEmmanuel Vadot <&clks IMX6QDL_CLK_GPU2D_AXI>, 120*c66ec88fSEmmanuel Vadot <&clks IMX6QDL_CLK_OPENVG_AXI>, 121*c66ec88fSEmmanuel Vadot <&clks IMX6QDL_CLK_VPU_AXI>; 122*c66ec88fSEmmanuel Vadot }; 123*c66ec88fSEmmanuel Vadot }; 124*c66ec88fSEmmanuel Vadot }; 125