1QCOM CPR (Core Power Reduction) 2 3CPR (Core Power Reduction) is a technology to reduce core power on a CPU 4or other device. Each OPP of a device corresponds to a "corner" that has 5a range of valid voltages for a particular frequency. While the device is 6running at a particular frequency, CPR monitors dynamic factors such as 7temperature, etc. and suggests adjustments to the voltage to save power 8and meet silicon characteristic requirements. 9 10- compatible: 11 Usage: required 12 Value type: <string> 13 Definition: should be "qcom,qcs404-cpr", "qcom,cpr" for qcs404 14 15- reg: 16 Usage: required 17 Value type: <prop-encoded-array> 18 Definition: base address and size of the rbcpr register region 19 20- interrupts: 21 Usage: required 22 Value type: <prop-encoded-array> 23 Definition: should specify the CPR interrupt 24 25- clocks: 26 Usage: required 27 Value type: <prop-encoded-array> 28 Definition: phandle to the reference clock 29 30- clock-names: 31 Usage: required 32 Value type: <stringlist> 33 Definition: must be "ref" 34 35- vdd-apc-supply: 36 Usage: required 37 Value type: <phandle> 38 Definition: phandle to the vdd-apc-supply regulator 39 40- #power-domain-cells: 41 Usage: required 42 Value type: <u32> 43 Definition: should be 0 44 45- operating-points-v2: 46 Usage: required 47 Value type: <phandle> 48 Definition: A phandle to the OPP table containing the 49 performance states supported by the CPR 50 power domain 51 52- acc-syscon: 53 Usage: optional 54 Value type: <phandle> 55 Definition: phandle to syscon for writing ACC settings 56 57- nvmem-cells: 58 Usage: required 59 Value type: <phandle> 60 Definition: phandle to nvmem cells containing the data 61 that makes up a fuse corner, for each fuse corner. 62 As well as the CPR fuse revision. 63 64- nvmem-cell-names: 65 Usage: required 66 Value type: <stringlist> 67 Definition: should be "cpr_quotient_offset1", "cpr_quotient_offset2", 68 "cpr_quotient_offset3", "cpr_init_voltage1", 69 "cpr_init_voltage2", "cpr_init_voltage3", "cpr_quotient1", 70 "cpr_quotient2", "cpr_quotient3", "cpr_ring_osc1", 71 "cpr_ring_osc2", "cpr_ring_osc3", "cpr_fuse_revision" 72 for qcs404. 73 74Example: 75 76 cpr_opp_table: cpr-opp-table { 77 compatible = "operating-points-v2-qcom-level"; 78 79 cpr_opp1: opp1 { 80 opp-level = <1>; 81 qcom,opp-fuse-level = <1>; 82 }; 83 cpr_opp2: opp2 { 84 opp-level = <2>; 85 qcom,opp-fuse-level = <2>; 86 }; 87 cpr_opp3: opp3 { 88 opp-level = <3>; 89 qcom,opp-fuse-level = <3>; 90 }; 91 }; 92 93 power-controller@b018000 { 94 compatible = "qcom,qcs404-cpr", "qcom,cpr"; 95 reg = <0x0b018000 0x1000>; 96 interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; 97 clocks = <&xo_board>; 98 clock-names = "ref"; 99 vdd-apc-supply = <&pms405_s3>; 100 #power-domain-cells = <0>; 101 operating-points-v2 = <&cpr_opp_table>; 102 acc-syscon = <&tcsr>; 103 104 nvmem-cells = <&cpr_efuse_quot_offset1>, 105 <&cpr_efuse_quot_offset2>, 106 <&cpr_efuse_quot_offset3>, 107 <&cpr_efuse_init_voltage1>, 108 <&cpr_efuse_init_voltage2>, 109 <&cpr_efuse_init_voltage3>, 110 <&cpr_efuse_quot1>, 111 <&cpr_efuse_quot2>, 112 <&cpr_efuse_quot3>, 113 <&cpr_efuse_ring1>, 114 <&cpr_efuse_ring2>, 115 <&cpr_efuse_ring3>, 116 <&cpr_efuse_revision>; 117 nvmem-cell-names = "cpr_quotient_offset1", 118 "cpr_quotient_offset2", 119 "cpr_quotient_offset3", 120 "cpr_init_voltage1", 121 "cpr_init_voltage2", 122 "cpr_init_voltage3", 123 "cpr_quotient1", 124 "cpr_quotient2", 125 "cpr_quotient3", 126 "cpr_ring_osc1", 127 "cpr_ring_osc2", 128 "cpr_ring_osc3", 129 "cpr_fuse_revision"; 130 }; 131