xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/toshiba,visconti-pinctrl.yaml (revision b197d4b893974c9eb4d7b38704c6d5c486235d6f) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/toshiba,visconti-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Toshiba Visconti TMPV770x pin mux/config controller
8
9maintainers:
10  - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
11
12description:
13  Toshiba's Visconti ARM SoC a pin mux/config controller.
14
15properties:
16  compatible:
17    enum:
18      - toshiba,tmpv7708-pinctrl
19
20  reg:
21    maxItems: 1
22
23allOf:
24  - $ref: "pinctrl.yaml#"
25
26required:
27  - compatible
28  - reg
29
30patternProperties:
31  '-pins$':
32    type: object
33    description: |
34      A pinctrl node should contain at least one subnodes representing the
35      pinctrl groups available on the machine. Each subnode will list the
36      pins it needs, and how they should be configured, with regard to muxer
37      configuration, pullups, drive strength.
38    $ref: "pinmux-node.yaml"
39
40    properties:
41      function:
42        description:
43          Function to mux.
44        $ref: "/schemas/types.yaml#/definitions/string"
45        enum: [i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8,
46               spi0, spi1, spi2, spi3, spi4, spi5, spi6,
47               uart0, uart1, uart2, uart3, pwm, pcmif_out, pcmif_in]
48
49      groups:
50        description:
51          Name of the pin group to use for the functions.
52        $ref: "/schemas/types.yaml#/definitions/string"
53        enum: [i2c0_grp, i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp,
54               i2c5_grp, i2c6_grp, i2c7_grp, i2c8_grp,
55               spi0_grp, spi0_cs0_grp, spi0_cs1_grp, spi0_cs2_grp,
56               spi1_grp, spi2_grp, spi3_grp, spi4_grp, spi5_grp, spi6_grp,
57               uart0_grp, uart1_grp, uart2_grp, uart3_grp,
58               pwm0_gpio4_grp, pwm0_gpio8_grp, pwm0_gpio12_grp,
59               pwm0_gpio16_grp, pwm1_gpio5_grp, pwm1_gpio9_grp,
60               pwm1_gpio13_grp, pwm1_gpio17_grp, pwm2_gpio6_grp,
61               pwm2_gpio10_grp, pwm2_gpio14_grp, pwm2_gpio18_grp,
62               pwm3_gpio7_grp, pwm3_gpio11_grp, pwm3_gpio15_grp,
63               pwm3_gpio19_grp, pcmif_out_grp, pcmif_in_grp]
64
65      drive-strength:
66        enum: [2, 4, 6, 8, 16, 24, 32]
67        default: 2
68        description:
69          Selects the drive strength for the specified pins, in mA.
70
71      bias-pull-up: true
72
73      bias-pull-down: true
74
75      bias-disable: true
76
77additionalProperties: false
78
79examples:
80  # Pinmux controller node
81  - |
82    soc {
83        #address-cells = <2>;
84        #size-cells = <2>;
85
86        pmux: pinmux@24190000 {
87            compatible = "toshiba,tmpv7708-pinctrl";
88            reg = <0 0x24190000 0 0x10000>;
89
90            spi0_pins: spi0-pins {
91                function = "spi0";
92                groups = "spi0_grp";
93            };
94        };
95    };
96