1*c66ec88fSEmmanuel Vadot* Pin configuration for TI IODELAY controller 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotTI dra7 based SoCs such as am57xx have a controller for setting the IO delay 4*c66ec88fSEmmanuel Vadotfor each pin. For most part the IO delay values are programmed by the bootloader, 5*c66ec88fSEmmanuel Vadotbut some pins need to be configured dynamically by the kernel such as the 6*c66ec88fSEmmanuel VadotMMC pins. 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel VadotRequired Properties: 9*c66ec88fSEmmanuel Vadot 10*c66ec88fSEmmanuel Vadot - compatible: Must be "ti,dra7-iodelay" 11*c66ec88fSEmmanuel Vadot - reg: Base address and length of the memory resource used 12*c66ec88fSEmmanuel Vadot - #address-cells: Number of address cells 13*c66ec88fSEmmanuel Vadot - #size-cells: Size of cells 14*c66ec88fSEmmanuel Vadot - #pinctrl-cells: Number of pinctrl cells, must be 2. See also 15*c66ec88fSEmmanuel Vadot Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 16*c66ec88fSEmmanuel Vadot 17*c66ec88fSEmmanuel VadotExample 18*c66ec88fSEmmanuel Vadot------- 19*c66ec88fSEmmanuel Vadot 20*c66ec88fSEmmanuel VadotIn the SoC specific dtsi file: 21*c66ec88fSEmmanuel Vadot 22*c66ec88fSEmmanuel Vadot dra7_iodelay_core: padconf@4844a000 { 23*c66ec88fSEmmanuel Vadot compatible = "ti,dra7-iodelay"; 24*c66ec88fSEmmanuel Vadot reg = <0x4844a000 0x0d1c>; 25*c66ec88fSEmmanuel Vadot #address-cells = <1>; 26*c66ec88fSEmmanuel Vadot #size-cells = <0>; 27*c66ec88fSEmmanuel Vadot #pinctrl-cells = <2>; 28*c66ec88fSEmmanuel Vadot }; 29*c66ec88fSEmmanuel Vadot 30*c66ec88fSEmmanuel VadotIn board-specific file: 31*c66ec88fSEmmanuel Vadot 32*c66ec88fSEmmanuel Vadot&dra7_iodelay_core { 33*c66ec88fSEmmanuel Vadot mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf { 34*c66ec88fSEmmanuel Vadot pinctrl-pin-array = < 35*c66ec88fSEmmanuel Vadot 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ 36*c66ec88fSEmmanuel Vadot 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ 37*c66ec88fSEmmanuel Vadot 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ 38*c66ec88fSEmmanuel Vadot 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ 39*c66ec88fSEmmanuel Vadot 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ 40*c66ec88fSEmmanuel Vadot 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ 41*c66ec88fSEmmanuel Vadot 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ 42*c66ec88fSEmmanuel Vadot 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ 43*c66ec88fSEmmanuel Vadot 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ 44*c66ec88fSEmmanuel Vadot 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ 45*c66ec88fSEmmanuel Vadot >; 46*c66ec88fSEmmanuel Vadot }; 47*c66ec88fSEmmanuel Vadot}; 48