1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (C) Sunplus Co., Ltd. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Sunplus SP7021 Pin Controller 9 10maintainers: 11 - Dvorkin Dmitry <dvorkin@tibbo.com> 12 - Wells Lu <wellslutw@gmail.com> 13 14description: | 15 The Sunplus SP7021 pin controller is used to control SoC pins. Please 16 refer to pinctrl-bindings.txt in this directory for details of the common 17 pinctrl bindings used by client devices. 18 19 SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All 20 are multiplexed with some special function pins. SP7021 has 3 types of 21 special function pins: 22 23 (1) function-group pins: 24 Ex 1 (SPI-NOR flash): 25 If control-field SPI_FLASH_SEL is set to 1, GPIO 83, 84, 86 and 87 26 will be pins of SPI-NOR flash. If it is set to 2, GPIO 76, 78, 79 27 and 81 will be pins of SPI-NOR flash. 28 29 Ex 2 (UART_0): 30 If control-bit UA0_SEL is set to 1, GPIO 88 and 89 will be TX and 31 RX pins of UART_0 (UART channel 0). 32 33 Ex 3 (eMMC): 34 If control-bit EMMC_SEL is set to 1, GPIO 72, 73, 74, 75, 76, 77, 35 78, 79, 80, 81 will be pins of an eMMC device. 36 37 Properties "function" and "groups" are used to select function-group 38 pins. 39 40 (2) fully pin-mux (like phone exchange mux) pins: 41 GPIO 8 to 71 are 'fully pin-mux' pins. Any pins of peripherals of 42 SP7021 (ex: UART_1, UART_2, UART_3, UART_4, I2C_0, I2C_1, and etc.) 43 can be routed to any pins of fully pin-mux pins. 44 45 Ex 1 (UART channel 1): 46 If control-field UA1_TX_SEL is set to 3, TX pin of UART_1 will be 47 routed to GPIO 10 (3 - 1 + 8 = 10). 48 If control-field UA1_RX_SEL is set to 4, RX pin of UART_1 will be 49 routed to GPIO 11 (4 - 1 + 8 = 11). 50 If control-field UA1_RTS_SEL is set to 5, RTS pin of UART_1 will 51 be routed to GPIO 12 (5 - 1 + 8 = 12). 52 If control-field UA1_CTS_SEL is set to 6, CTS pin of UART_1 will 53 be routed to GPIO 13 (6 - 1 + 8 = 13). 54 55 Ex 2 (I2C channel 0): 56 If control-field I2C0_CLK_SEL is set to 20, CLK pin of I2C_0 will 57 be routed to GPIO 27 (20 - 1 + 8 = 27). 58 If control-field I2C0_DATA_SEL is set to 21, DATA pin of I2C_0 59 will be routed to GPIO 28 (21 - 1 + 9 = 28). 60 61 Totally, SP7021 has 120 peripheral pins. The peripheral pins can be 62 routed to any of 64 'fully pin-mux' pins. 63 64 (3) I/O processor pins 65 SP7021 has a built-in I/O processor. 66 Any GPIO pins (GPIO 0 to 98) can be set to pins of I/O processor. 67 68 Vendor property "sunplus,pins" is used to select "fully pin-mux" pins, 69 "I/O processor pins" and "digital GPIO" pins. 70 71 The device node of pin controller of Sunplus SP7021 has following 72 properties. 73 74properties: 75 compatible: 76 const: sunplus,sp7021-pctl 77 78 gpio-controller: true 79 80 '#gpio-cells': 81 const: 2 82 83 reg: 84 items: 85 - description: the MOON2 registers 86 - description: the GPIOXT registers 87 - description: the FIRST registers 88 - description: the MOON1 registers 89 90 reg-names: 91 items: 92 - const: moon2 93 - const: gpioxt 94 - const: first 95 - const: moon1 96 97 clocks: 98 maxItems: 1 99 100 resets: 101 maxItems: 1 102 103patternProperties: 104 '-pins$': 105 type: object 106 description: | 107 A pinctrl node should contain at least one subnodes representing the 108 pins or function-pins group available on the machine. Each subnode 109 will list the pins it needs, and how they should be configured. 110 111 Pinctrl node's client devices use subnodes for desired pin 112 configuration. Client device subnodes use below standard properties. 113 $ref: pinmux-node.yaml# 114 115 properties: 116 sunplus,pins: 117 description: | 118 Define 'sunplus,pins' which are used by pinctrl node's client 119 device. 120 121 It consists of one or more integers which represents the config 122 setting for corresponding pin. Each integer defines a individual 123 pin in which: 124 125 Bit 32~24: defines GPIO number. Its range is 0 ~ 98. 126 Bit 23~16: defines types: (1) fully pin-mux pins 127 (2) IO processor pins 128 (3) digital GPIO pins 129 Bit 15~8: defines pins of peripherals (which are defined in 130 'include/dt-binging/pinctrl/sppctl.h'). 131 Bit 7~0: defines types or initial-state of digital GPIO pins. 132 133 Please use macro SPPCTL_IOPAD to define the integers for pins. 134 135 $ref: /schemas/types.yaml#/definitions/uint32-array 136 137 function: 138 description: | 139 Define pin-function which is used by pinctrl node's client device. 140 The name should be one of string in the following enumeration. 141 $ref: /schemas/types.yaml#/definitions/string 142 enum: [ SPI_FLASH, SPI_FLASH_4BIT, SPI_NAND, CARD0_EMMC, SD_CARD, 143 UA0, FPGA_IFX, HDMI_TX, LCDIF, USB0_OTG, USB1_OTG ] 144 145 groups: 146 description: | 147 Define pin-group in a specified pin-function. 148 The name should be one of string in the following enumeration. 149 $ref: /schemas/types.yaml#/definitions/string 150 enum: [ SPI_FLASH1, SPI_FLASH2, SPI_FLASH_4BIT1, SPI_FLASH_4BIT2, 151 SPI_NAND, CARD0_EMMC, SD_CARD, UA0, FPGA_IFX, HDMI_TX1, 152 HDMI_TX2, HDMI_TX3, LCDIF, USB0_OTG, USB1_OTG ] 153 154 sunplus,zerofunc: 155 description: | 156 This is a vendor specific property. It is used to disable pins 157 which are not used by pinctrl node's client device. 158 Some pins may be enabled by boot-loader. We can use this 159 property to disable them. 160 $ref: /schemas/types.yaml#/definitions/uint32-array 161 162 additionalProperties: false 163 164 allOf: 165 - if: 166 properties: 167 function: 168 enum: 169 - SPI_FLASH 170 then: 171 properties: 172 groups: 173 enum: 174 - SPI_FLASH1 175 - SPI_FLASH2 176 - if: 177 properties: 178 function: 179 enum: 180 - SPI_FLASH_4BIT 181 then: 182 properties: 183 groups: 184 enum: 185 - SPI_FLASH_4BIT1 186 - SPI_FLASH_4BIT2 187 - if: 188 properties: 189 function: 190 enum: 191 - SPI_NAND 192 then: 193 properties: 194 groups: 195 enum: 196 - SPI_NAND 197 - if: 198 properties: 199 function: 200 enum: 201 - CARD0_EMMC 202 then: 203 properties: 204 groups: 205 enum: 206 - CARD0_EMMC 207 - if: 208 properties: 209 function: 210 enum: 211 - SD_CARD 212 then: 213 properties: 214 groups: 215 enum: 216 - SD_CARD 217 - if: 218 properties: 219 function: 220 enum: 221 - UA0 222 then: 223 properties: 224 groups: 225 enum: 226 - UA0 227 - if: 228 properties: 229 function: 230 enum: 231 - FPGA_IFX 232 then: 233 properties: 234 groups: 235 enum: 236 - FPGA_IFX 237 - if: 238 properties: 239 function: 240 enum: 241 - HDMI_TX 242 then: 243 properties: 244 groups: 245 enum: 246 - HDMI_TX1 247 - HDMI_TX2 248 - HDMI_TX3 249 - if: 250 properties: 251 function: 252 enum: 253 - LCDIF 254 then: 255 properties: 256 groups: 257 enum: 258 - LCDIF 259 - if: 260 properties: 261 function: 262 enum: 263 - USB0_OTG 264 then: 265 properties: 266 groups: 267 enum: 268 - USB0_OTG 269 - if: 270 properties: 271 function: 272 enum: 273 - USB1_OTG 274 then: 275 properties: 276 groups: 277 enum: 278 - USB1_OTG 279 280required: 281 - compatible 282 - reg 283 - reg-names 284 - "#gpio-cells" 285 - gpio-controller 286 - clocks 287 - resets 288 289additionalProperties: false 290 291allOf: 292 - $ref: pinctrl.yaml# 293 294examples: 295 - | 296 #include <dt-bindings/pinctrl/sppctl-sp7021.h> 297 298 pinctrl@9c000100 { 299 compatible = "sunplus,sp7021-pctl"; 300 reg = <0x9c000100 0x100>, <0x9c000300 0x100>, 301 <0x9c0032e4 0x1c>, <0x9c000080 0x20>; 302 reg-names = "moon2", "gpioxt", "first", "moon1"; 303 gpio-controller; 304 #gpio-cells = <2>; 305 clocks = <&clkc 0x83>; 306 resets = <&rstc 0x73>; 307 308 uart0-pins { 309 function = "UA0"; 310 groups = "UA0"; 311 }; 312 313 spinand0-pins { 314 function = "SPI_NAND"; 315 groups = "SPI_NAND"; 316 }; 317 318 uart1-pins { 319 sunplus,pins = < 320 SPPCTL_IOPAD(11, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0) 321 SPPCTL_IOPAD(10, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0) 322 >; 323 }; 324 325 uart2-pins { 326 sunplus,pins = < 327 SPPCTL_IOPAD(20, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0) 328 SPPCTL_IOPAD(21, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0) 329 SPPCTL_IOPAD(22, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RTS, 0) 330 SPPCTL_IOPAD(23, SPPCTL_PCTL_G_PMUX, MUXF_UA1_CTS, 0) 331 >; 332 }; 333 334 emmc-pins { 335 function = "CARD0_EMMC"; 336 groups = "CARD0_EMMC"; 337 }; 338 339 sdcard-pins { 340 function = "SD_CARD"; 341 groups = "SD_CARD"; 342 sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >; 343 }; 344 345 hdmi_A_tx1-pins { 346 function = "HDMI_TX"; 347 groups = "HDMI_TX1"; 348 }; 349 hdmi_A_tx2-pins { 350 function = "HDMI_TX"; 351 groups = "HDMI_TX2"; 352 }; 353 hdmi_A_tx3-pins { 354 function = "HDMI_TX"; 355 groups = "HDMI_TX3"; 356 }; 357 358 ethernet-pins { 359 sunplus,pins = < 360 SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0) 361 SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0) 362 SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0) 363 SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0) 364 SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0) 365 SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0) 366 SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0) 367 SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0) 368 SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0) 369 >; 370 sunplus,zerofunc = < 371 MUXF_L2SW_LED_FLASH0 372 MUXF_L2SW_LED_ON0 373 MUXF_L2SW_P0_MAC_RMII_RXER 374 >; 375 }; 376 }; 377... 378