1Samsung GPIO and Pin Mux/Config controller 2 3Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware 4controller. It controls the input/output settings on the available pads/pins 5and also provides ability to multiplex and configure the output of various 6on-chip controllers onto these pads. 7 8Required Properties: 9- compatible: should be one of the following. 10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller, 11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller, 12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller, 13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller, 14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller, 15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller, 16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller. 17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. 18 - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. 19 - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. 20 - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. 21 - "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller. 22 - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. 23 - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller. 24 - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. 25 - "samsung,exynos7885-pinctrl": for Exynos7885 compatible pin-controller. 26 - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller. 27 - "samsung,exynosautov9-pinctrl": for ExynosAutov9 compatible pin-controller. 28 29- reg: Base address of the pin controller hardware module and length of 30 the address space it occupies. 31 32 - reg: Second base address of the pin controller if the specific registers 33 of the pin controller are separated into the different base address. 34 35 Eg: GPF[1-5] of Exynos5433 are separated into the two base address. 36 - First base address is for GPAx and GPF[1-5] external interrupt 37 registers. 38 - Second base address is for GPF[1-5] pinctrl registers. 39 40 pinctrl_0: pinctrl@10580000 { 41 compatible = "samsung,exynos5433-pinctrl"; 42 reg = <0x10580000 0x1a20>, <0x11090000 0x100>; 43 44 wakeup-interrupt-controller { 45 compatible = "samsung,exynos7-wakeup-eint"; 46 interrupts = <0 16 0>; 47 }; 48 }; 49 50- Pin banks as child nodes: Pin banks of the controller are represented by child 51 nodes of the controller node. Bank name is taken from name of the node. Each 52 bank node must contain following properties: 53 54 - gpio-controller: identifies the node as a gpio controller and pin bank. 55 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO 56 binding is used, the amount of cells must be specified as 2. See the below 57 mentioned gpio binding representation for description of particular cells. 58 59 Eg: <&gpx2 6 0> 60 <[phandle of the gpio controller node] 61 [pin number within the gpio controller] 62 [flags]> 63 64 Values for gpio specifier: 65 - Pin number: is a value between 0 to 7. 66 - Flags: 0 - Active High 67 1 - Active Low 68 69- Pin mux/config groups as child nodes: The pin mux (selecting pin function 70 mode) and pin config (pull up/down, driver strength) settings are represented 71 as child nodes of the pin-controller node. There should be at least one 72 child node and there is no limit on the count of these child nodes. It is 73 also possible for a child node to consist of several further child nodes 74 to allow grouping multiple pinctrl groups into one. The format of second 75 level child nodes is exactly the same as for first level ones and is 76 described below. 77 78 The child node should contain a list of pin(s) on which a particular pin 79 function selection or pin configuration (or both) have to applied. This 80 list of pins is specified using the property name "samsung,pins". There 81 should be at least one pin specified for this property and there is no upper 82 limit on the count of pins that can be specified. The pins are specified 83 using pin names which are derived from the hardware manual of the SoC. As 84 an example, the pins in GPA0 bank of the pin controller can be represented 85 as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case. 86 The format of the pin names should be (as per the hardware manual) 87 "[pin bank name]-[pin number within the bank]". 88 89 The pin function selection that should be applied on the pins listed in the 90 child node is specified using the "samsung,pin-function" property. The value 91 of this property that should be applied to each of the pins listed in the 92 "samsung,pins" property should be picked from the hardware manual of the SoC 93 for the specified pin group. This property is optional in the child node if 94 no specific function selection is desired for the pins listed in the child 95 node. The value of this property is used as-is to program the pin-controller 96 function selector register of the pin-bank. 97 98 The child node can also optionally specify one or more of the pin 99 configuration that should be applied on all the pins listed in the 100 "samsung,pins" property of the child node. The following pin configuration 101 properties are supported. 102 103 - samsung,pin-val: Initial value of pin output buffer. 104 - samsung,pin-pud: Pull up/down configuration. 105 - samsung,pin-drv: Drive strength configuration. 106 - samsung,pin-pud-pdn: Pull up/down configuration in power down mode. 107 - samsung,pin-drv-pdn: Drive strength configuration in power down mode. 108 109 The values specified by these config properties should be derived from the 110 hardware manual and these values are programmed as-is into the pin 111 pull up/down and driver strength register of the pin-controller. 112 113 Note: A child should include at least a pin function selection property or 114 pin configuration property (one or more) or both. 115 116 The client nodes that require a particular pin function selection and/or 117 pin configuration should use the bindings listed in the "pinctrl-bindings.txt" 118 file. 119 120External GPIO and Wakeup Interrupts: 121 122The controller supports two types of external interrupts over gpio. The first 123is the external gpio interrupt and second is the external wakeup interrupts. 124The difference between the two is that the external wakeup interrupts can be 125used as system wakeup events. 126 127A. External GPIO Interrupts: For supporting external gpio interrupts, the 128 following properties should be specified in the pin-controller device node. 129 130 - interrupts: interrupt specifier for the controller. The format and value of 131 the interrupt specifier depends on the interrupt parent for the controller. 132 133 In addition, following properties must be present in node of every bank 134 of pins supporting GPIO interrupts: 135 136 - interrupt-controller: identifies the controller node as interrupt-parent. 137 - #interrupt-cells: the value of this property should be 2. 138 - First Cell: represents the external gpio interrupt number local to the 139 external gpio interrupt space of the controller. 140 - Second Cell: flags to identify the type of the interrupt 141 - 1 = rising edge triggered 142 - 2 = falling edge triggered 143 - 3 = rising and falling edge triggered 144 - 4 = high level triggered 145 - 8 = low level triggered 146 147B. External Wakeup Interrupts: For supporting external wakeup interrupts, a 148 child node representing the external wakeup interrupt controller should be 149 included in the pin-controller device node. 150 151 Only one pin-controller device node can include external wakeup interrupts 152 child node (in other words, only one External Wakeup Interrupts 153 pin-controller is supported). 154 155 This child node should include following properties: 156 157 - compatible: identifies the type of the external wakeup interrupt controller 158 The possible values are: 159 - samsung,s3c2410-wakeup-eint: represents wakeup interrupt controller 160 found on Samsung S3C24xx SoCs except S3C2412 and S3C2413, 161 - samsung,s3c2412-wakeup-eint: represents wakeup interrupt controller 162 found on Samsung S3C2412 and S3C2413 SoCs, 163 - samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller 164 found on Samsung S3C64xx SoCs, 165 - samsung,s5pv210-wakeup-eint: represents wakeup interrupt controller 166 found on Samsung S5Pv210 SoCs, 167 - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller 168 found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs. 169 - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller 170 found on Samsung Exynos7 SoC. 171 - interrupts: interrupt used by multiplexed wakeup interrupts. 172 173 In addition, following properties must be present in node of every bank 174 of pins supporting wake-up interrupts: 175 176 - interrupt-controller: identifies the node as interrupt-parent. 177 - #interrupt-cells: the value of this property should be 2 178 - First Cell: represents the external wakeup interrupt number local to 179 the external wakeup interrupt space of the controller. 180 - Second Cell: flags to identify the type of the interrupt 181 - 1 = rising edge triggered 182 - 2 = falling edge triggered 183 - 3 = rising and falling edge triggered 184 - 4 = high level triggered 185 - 8 = low level triggered 186 187 Node of every bank of pins supporting direct wake-up interrupts (without 188 multiplexing) must contain following properties: 189 190 - interrupts: interrupts of the interrupt parent which are used for external 191 wakeup interrupts from pins of the bank, must contain interrupts for all 192 pins of the bank. 193 194Aliases: 195 196All the pin controller nodes should be represented in the aliases node using 197the following format 'pinctrl{n}' where n is a unique number for the alias. 198 199Aliases for controllers compatible with "samsung,exynos7-pinctrl": 200- pinctrl0: pin controller of ALIVE block, 201- pinctrl1: pin controller of BUS0 block, 202- pinctrl2: pin controller of NFC block, 203- pinctrl3: pin controller of TOUCH block, 204- pinctrl4: pin controller of FF block, 205- pinctrl5: pin controller of ESE block, 206- pinctrl6: pin controller of FSYS0 block, 207- pinctrl7: pin controller of FSYS1 block, 208- pinctrl8: pin controller of BUS1 block, 209- pinctrl9: pin controller of AUDIO block, 210 211Example: A pin-controller node with pin banks: 212 213 pinctrl_0: pinctrl@11400000 { 214 compatible = "samsung,exynos4210-pinctrl"; 215 reg = <0x11400000 0x1000>; 216 interrupts = <0 47 0>; 217 218 /* ... */ 219 220 /* Pin bank without external interrupts */ 221 gpy0: gpy0 { 222 gpio-controller; 223 #gpio-cells = <2>; 224 }; 225 226 /* ... */ 227 228 /* Pin bank with external GPIO or muxed wake-up interrupts */ 229 gpj0: gpj0 { 230 gpio-controller; 231 #gpio-cells = <2>; 232 233 interrupt-controller; 234 #interrupt-cells = <2>; 235 }; 236 237 /* ... */ 238 239 /* Pin bank with external direct wake-up interrupts */ 240 gpx0: gpx0 { 241 gpio-controller; 242 #gpio-cells = <2>; 243 244 interrupt-controller; 245 interrupt-parent = <&gic>; 246 interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, 247 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; 248 #interrupt-cells = <2>; 249 }; 250 251 /* ... */ 252 }; 253 254Example 1: A pin-controller node with pin groups. 255 256 #include <dt-bindings/pinctrl/samsung.h> 257 258 pinctrl_0: pinctrl@11400000 { 259 compatible = "samsung,exynos4210-pinctrl"; 260 reg = <0x11400000 0x1000>; 261 interrupts = <0 47 0>; 262 263 /* ... */ 264 265 uart0_data: uart0-data { 266 samsung,pins = "gpa0-0", "gpa0-1"; 267 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 268 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 269 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 270 }; 271 272 uart0_fctl: uart0-fctl { 273 samsung,pins = "gpa0-2", "gpa0-3"; 274 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 275 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 276 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 277 }; 278 279 uart1_data: uart1-data { 280 samsung,pins = "gpa0-4", "gpa0-5"; 281 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 282 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 283 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 284 }; 285 286 uart1_fctl: uart1-fctl { 287 samsung,pins = "gpa0-6", "gpa0-7"; 288 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 289 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 290 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 291 }; 292 293 i2c2_bus: i2c2-bus { 294 samsung,pins = "gpa0-6", "gpa0-7"; 295 samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 296 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 297 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 298 }; 299 300 sd4_bus8: sd4-bus-width8 { 301 part-1 { 302 samsung,pins = "gpk0-3", "gpk0-4", 303 "gpk0-5", "gpk0-6"; 304 samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 305 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 306 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 307 }; 308 part-2 { 309 samsung,pins = "gpk1-3", "gpk1-4", 310 "gpk1-5", "gpk1-6"; 311 samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 312 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 313 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 314 }; 315 }; 316 }; 317 318Example 2: A pin-controller node with external wakeup interrupt controller node. 319 320 pinctrl_1: pinctrl@11000000 { 321 compatible = "samsung,exynos4210-pinctrl"; 322 reg = <0x11000000 0x1000>; 323 interrupts = <0 46 0> 324 325 /* ... */ 326 327 wakeup-interrupt-controller { 328 compatible = "samsung,exynos4210-wakeup-eint"; 329 interrupt-parent = <&gic>; 330 interrupts = <0 32 0>; 331 }; 332 }; 333 334Example 3: A uart client node that supports 'default' and 'flow-control' states. 335 336 uart@13800000 { 337 compatible = "samsung,exynos4210-uart"; 338 reg = <0x13800000 0x100>; 339 interrupts = <0 52 0>; 340 pinctrl-names = "default", "flow-control; 341 pinctrl-0 = <&uart0_data>; 342 pinctrl-1 = <&uart0_data>, <&uart0_fctl>; 343 }; 344 345Example 4: Set up the default pin state for uart controller. 346 347 static int s3c24xx_serial_probe(struct platform_device *pdev) { 348 struct pinctrl *pinctrl; 349 350 /* ... */ 351 352 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 353 } 354 355Example 5: A display port client node that supports 'default' pinctrl state 356 and gpio binding. 357 358 display-port-controller { 359 /* ... */ 360 361 samsung,hpd-gpio = <&gpx2 6 0>; 362 pinctrl-names = "default"; 363 pinctrl-0 = <&dp_hpd>; 364 }; 365 366Example 6: Request the gpio for display port controller 367 368 static int exynos_dp_probe(struct platform_device *pdev) 369 { 370 int hpd_gpio, ret; 371 struct device *dev = &pdev->dev; 372 struct device_node *dp_node = dev->of_node; 373 374 /* ... */ 375 376 hpd_gpio = of_get_named_gpio(dp_node, "samsung,hpd-gpio", 0); 377 378 /* ... */ 379 380 ret = devm_gpio_request_one(&pdev->dev, hpd_gpio, GPIOF_IN, 381 "hpd_gpio"); 382 /* ... */ 383 } 384