1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip Pinmux Controller 8 9maintainers: 10 - Heiko Stuebner <heiko@sntech.de> 11 12description: | 13 The Rockchip Pinmux Controller enables the IC to share one PAD 14 to several functional blocks. The sharing is done by multiplexing 15 the PAD input/output signals. For each PAD there are several muxing 16 options with option 0 being used as a GPIO. 17 18 Please refer to pinctrl-bindings.txt in this directory for details of the 19 common pinctrl bindings used by client devices, including the meaning of the 20 phrase "pin configuration node". 21 22 The Rockchip pin configuration node is a node of a group of pins which can be 23 used for a specific device or function. This node represents both mux and 24 config of the pins in that group. The 'pins' selects the function mode 25 (also named pin mode) this pin can work on and the 'config' configures 26 various pad settings such as pull-up, etc. 27 28 The pins are grouped into up to 9 individual pin banks which need to be 29 defined as gpio sub-nodes of the pinmux controller. 30 31properties: 32 compatible: 33 enum: 34 - rockchip,px30-pinctrl 35 - rockchip,rk2928-pinctrl 36 - rockchip,rk3036-pinctrl 37 - rockchip,rk3066a-pinctrl 38 - rockchip,rk3066b-pinctrl 39 - rockchip,rk3128-pinctrl 40 - rockchip,rk3188-pinctrl 41 - rockchip,rk3228-pinctrl 42 - rockchip,rk3288-pinctrl 43 - rockchip,rk3308-pinctrl 44 - rockchip,rk3328-pinctrl 45 - rockchip,rk3368-pinctrl 46 - rockchip,rk3399-pinctrl 47 - rockchip,rk3568-pinctrl 48 - rockchip,rk3588-pinctrl 49 - rockchip,rv1108-pinctrl 50 - rockchip,rv1126-pinctrl 51 52 rockchip,grf: 53 $ref: /schemas/types.yaml#/definitions/phandle 54 description: 55 The phandle of the syscon node for the GRF registers. 56 57 rockchip,pmu: 58 $ref: /schemas/types.yaml#/definitions/phandle 59 description: 60 The phandle of the syscon node for the PMU registers, 61 as some SoCs carry parts of the iomux controller registers there. 62 Required for at least rk3188 and rk3288. On the rk3368 this should 63 point to the PMUGRF syscon. 64 65 "#address-cells": 66 enum: [1, 2] 67 68 "#size-cells": 69 enum: [1, 2] 70 71 ranges: true 72 73allOf: 74 - $ref: pinctrl.yaml# 75 76required: 77 - compatible 78 - rockchip,grf 79 80patternProperties: 81 "gpio@[0-9a-f]+$": 82 type: object 83 84 $ref: /schemas/gpio/rockchip,gpio-bank.yaml# 85 deprecated: true 86 87 unevaluatedProperties: false 88 89 "pcfg-[a-z0-9-]+$": 90 type: object 91 properties: 92 bias-disable: true 93 94 bias-pull-down: true 95 96 bias-pull-pin-default: true 97 98 bias-pull-up: true 99 100 drive-strength: 101 minimum: 0 102 maximum: 20 103 104 input-enable: true 105 106 input-schmitt-enable: true 107 108 output-high: true 109 110 output-low: true 111 112 additionalProperties: false 113 114additionalProperties: 115 type: object 116 additionalProperties: 117 type: object 118 properties: 119 rockchip,pins: 120 $ref: /schemas/types.yaml#/definitions/uint32-matrix 121 minItems: 1 122 items: 123 items: 124 - minimum: 0 125 maximum: 8 126 description: 127 Pin bank. 128 - minimum: 0 129 maximum: 31 130 description: 131 Pin bank index. 132 - minimum: 0 133 maximum: 13 134 description: 135 Mux 0 means GPIO and mux 1 to N means 136 the specific device function. 137 - description: 138 The phandle of a node contains the generic pinconfig options 139 to use as described in pinctrl-bindings.txt. 140 141examples: 142 - | 143 #include <dt-bindings/interrupt-controller/arm-gic.h> 144 #include <dt-bindings/pinctrl/rockchip.h> 145 146 pinctrl: pinctrl { 147 compatible = "rockchip,rk3066a-pinctrl"; 148 rockchip,grf = <&grf>; 149 150 #address-cells = <1>; 151 #size-cells = <1>; 152 ranges; 153 154 gpio0: gpio@20034000 { 155 compatible = "rockchip,gpio-bank"; 156 reg = <0x20034000 0x100>; 157 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 158 clocks = <&clk_gates8 9>; 159 160 gpio-controller; 161 #gpio-cells = <2>; 162 163 interrupt-controller; 164 #interrupt-cells = <2>; 165 }; 166 167 pcfg_pull_default: pcfg-pull-default { 168 bias-pull-pin-default; 169 }; 170 171 uart2 { 172 uart2_xfer: uart2-xfer { 173 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, 174 <1 RK_PB1 1 &pcfg_pull_default>; 175 }; 176 }; 177 }; 178 179 uart2: serial@20064000 { 180 compatible = "snps,dw-apb-uart"; 181 reg = <0x20064000 0x400>; 182 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&mux_uart2>; 184 pinctrl-0 = <&uart2_xfer>; 185 pinctrl-names = "default"; 186 reg-io-width = <1>; 187 reg-shift = <2>; 188 }; 189