1* Rockchip Pinmux Controller 2 3The Rockchip Pinmux Controller, enables the IC 4to share one PAD to several functional blocks. The sharing is done by 5multiplexing the PAD input/output signals. For each PAD there are several 6muxing options with option 0 being the use as a GPIO. 7 8Please refer to pinctrl-bindings.txt in this directory for details of the 9common pinctrl bindings used by client devices, including the meaning of the 10phrase "pin configuration node". 11 12The Rockchip pin configuration node is a node of a group of pins which can be 13used for a specific device or function. This node represents both mux and 14config of the pins in that group. The 'pins' selects the function mode(also 15named pin mode) this pin can work on and the 'config' configures various pad 16settings such as pull-up, etc. 17 18The pins are grouped into up to 5 individual pin banks which need to be 19defined as gpio sub-nodes of the pinmux controller. 20 21Required properties for iomux controller: 22 - compatible: should be 23 "rockchip,px30-pinctrl": for Rockchip PX30 24 "rockchip,rv1108-pinctrl": for Rockchip RV1108 25 "rockchip,rk2928-pinctrl": for Rockchip RK2928 26 "rockchip,rk3066a-pinctrl": for Rockchip RK3066a 27 "rockchip,rk3066b-pinctrl": for Rockchip RK3066b 28 "rockchip,rk3128-pinctrl": for Rockchip RK3128 29 "rockchip,rk3188-pinctrl": for Rockchip RK3188 30 "rockchip,rk3228-pinctrl": for Rockchip RK3228 31 "rockchip,rk3288-pinctrl": for Rockchip RK3288 32 "rockchip,rk3308-pinctrl": for Rockchip RK3308 33 "rockchip,rk3328-pinctrl": for Rockchip RK3328 34 "rockchip,rk3368-pinctrl": for Rockchip RK3368 35 "rockchip,rk3399-pinctrl": for Rockchip RK3399 36 "rockchip,rk3568-pinctrl": for Rockchip RK3568 37 38 - rockchip,grf: phandle referencing a syscon providing the 39 "general register files" 40 41Optional properties for iomux controller: 42 - rockchip,pmu: phandle referencing a syscon providing the pmu registers 43 as some SoCs carry parts of the iomux controller registers there. 44 Required for at least rk3188 and rk3288. On the rk3368 this should 45 point to the PMUGRF syscon. 46 47Deprecated properties for iomux controller: 48 - reg: first element is the general register space of the iomux controller 49 It should be large enough to contain also separate pull registers. 50 second element is the separate pull register space of the rk3188. 51 Use rockchip,grf and rockchip,pmu described above instead. 52 53Required properties for gpio sub nodes: 54See rockchip,gpio-bank.yaml 55 56Required properties for pin configuration node: 57 - rockchip,pins: 3 integers array, represents a group of pins mux and config 58 setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>. 59 The MUX 0 means gpio and MUX 1 to N mean the specific device function. 60 The phandle of a node containing the generic pinconfig options 61 to use, as described in pinctrl-bindings.txt in this directory. 62 63Examples: 64 65#include <dt-bindings/pinctrl/rockchip.h> 66 67... 68 69pinctrl@20008000 { 70 compatible = "rockchip,rk3066a-pinctrl"; 71 rockchip,grf = <&grf>; 72 73 #address-cells = <1>; 74 #size-cells = <1>; 75 ranges; 76 77 gpio0: gpio0@20034000 { 78 compatible = "rockchip,gpio-bank"; 79 reg = <0x20034000 0x100>; 80 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 81 clocks = <&clk_gates8 9>; 82 83 gpio-controller; 84 #gpio-cells = <2>; 85 86 interrupt-controller; 87 #interrupt-cells = <2>; 88 }; 89 90 ... 91 92 pcfg_pull_default: pcfg_pull_default { 93 bias-pull-pin-default 94 }; 95 96 uart2 { 97 uart2_xfer: uart2-xfer { 98 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, 99 <1 RK_PB1 1 &pcfg_pull_default>; 100 }; 101 }; 102}; 103 104uart2: serial@20064000 { 105 compatible = "snps,dw-apb-uart"; 106 reg = <0x20064000 0x400>; 107 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 108 reg-shift = <2>; 109 reg-io-width = <1>; 110 clocks = <&mux_uart2>; 111 112 pinctrl-names = "default"; 113 pinctrl-0 = <&uart2_xfer>; 114}; 115