1Renesas RZ/N1 SoC Pinctrl node description. 2 3Pin controller node 4------------------- 5Required properties: 6- compatible: SoC-specific compatible string "renesas,<soc-specific>-pinctrl" 7 followed by "renesas,rzn1-pinctrl" as fallback. The SoC-specific compatible 8 strings must be one of: 9 "renesas,r9a06g032-pinctrl" for RZ/N1D 10 "renesas,r9a06g033-pinctrl" for RZ/N1S 11- reg: Address base and length of the memory area where the pin controller 12 hardware is mapped to. 13- clocks: phandle for the clock, see the description of clock-names below. 14- clock-names: Contains the name of the clock: 15 "bus", the bus clock, sometimes described as pclk, for register accesses. 16 17Example: 18 pinctrl: pin-controller@40067000 { 19 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; 20 reg = <0x40067000 0x1000>, <0x51000000 0x480>; 21 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; 22 clock-names = "bus"; 23 }; 24 25Sub-nodes 26--------- 27 28The child nodes of the pin controller node describe a pin multiplexing 29function. 30 31- Pin multiplexing sub-nodes: 32 A pin multiplexing sub-node describes how to configure a set of 33 (or a single) pin in some desired alternate function mode. 34 A single sub-node may define several pin configurations. 35 Please refer to pinctrl-bindings.txt to get to know more on generic 36 pin properties usage. 37 38 The allowed generic formats for a pin multiplexing sub-node are the 39 following ones: 40 41 node-1 { 42 pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ; 43 GENERIC_PINCONFIG; 44 }; 45 46 node-2 { 47 sub-node-1 { 48 pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ; 49 GENERIC_PINCONFIG; 50 }; 51 52 sub-node-2 { 53 pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ; 54 GENERIC_PINCONFIG; 55 }; 56 57 ... 58 59 sub-node-n { 60 pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ; 61 GENERIC_PINCONFIG; 62 }; 63 }; 64 65 node-3 { 66 pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ; 67 GENERIC_PINCONFIG; 68 69 sub-node-1 { 70 pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ; 71 GENERIC_PINCONFIG; 72 }; 73 74 ... 75 76 sub-node-n { 77 pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ; 78 GENERIC_PINCONFIG; 79 }; 80 }; 81 82 Use the latter two formats when pins part of the same logical group need to 83 have different generic pin configuration flags applied. Note that the generic 84 pinconfig in node-3 does not apply to the sub-nodes. 85 86 Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle 87 of the most external one. 88 89 Eg. 90 91 client-1 { 92 ... 93 pinctrl-0 = <&node-1>; 94 ... 95 }; 96 97 client-2 { 98 ... 99 pinctrl-0 = <&node-2>; 100 ... 101 }; 102 103 Required properties: 104 - pinmux: 105 integer array representing pin number and pin multiplexing configuration. 106 When a pin has to be configured in alternate function mode, use this 107 property to identify the pin by its global index, and provide its 108 alternate function configuration number along with it. 109 When multiple pins are required to be configured as part of the same 110 alternate function they shall be specified as members of the same 111 argument list of a single "pinmux" property. 112 Integers values in the "pinmux" argument list are assembled as: 113 (PIN | MUX_FUNC << 8) 114 where PIN directly corresponds to the pl_gpio pin number and MUX_FUNC is 115 one of the alternate function identifiers defined in: 116 <include/dt-bindings/pinctrl/rzn1-pinctrl.h> 117 These identifiers collapse the IO Multiplex Configuration Level 1 and 118 Level 2 numbers that are detailed in the hardware reference manual into a 119 single number. The identifiers for Level 2 are simply offset by 10. 120 Additional identifiers are provided to specify the MDIO source peripheral. 121 122 Optional generic pinconf properties: 123 - bias-disable - disable any pin bias 124 - bias-pull-up - pull up the pin with 50 KOhm 125 - bias-pull-down - pull down the pin with 50 KOhm 126 - bias-high-impedance - high impedance mode 127 - drive-strength - sink or source at most 4, 6, 8 or 12 mA 128 129 Example: 130 A serial communication interface with a TX output pin and an RX input pin. 131 132 &pinctrl { 133 pins_uart0: pins_uart0 { 134 pinmux = < 135 RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */ 136 RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */ 137 >; 138 }; 139 }; 140 141 Example 2: 142 Here we set the pull up on the RXD pin of the UART. 143 144 &pinctrl { 145 pins_uart0: pins_uart0 { 146 pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>; /* TXD */ 147 148 pins_uart6_rx { 149 pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>; /* RXD */ 150 bias-pull-up; 151 }; 152 }; 153 }; 154