1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SM8550 SoC LPASS LPI TLMM 8 9maintainers: 10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> 12 13description: 14 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem 15 (LPASS) Low Power Island (LPI) of Qualcomm SM8550 SoC. 16 17properties: 18 compatible: 19 const: qcom,sm8550-lpass-lpi-pinctrl 20 21 reg: 22 items: 23 - description: LPASS LPI TLMM Control and Status registers 24 - description: LPASS LPI MCC registers 25 26 clocks: 27 items: 28 - description: LPASS Core voting clock 29 - description: LPASS Audio voting clock 30 31 clock-names: 32 items: 33 - const: core 34 - const: audio 35 36 gpio-controller: true 37 38 "#gpio-cells": 39 description: Specifying the pin number and flags, as defined in 40 include/dt-bindings/gpio/gpio.h 41 const: 2 42 43 gpio-ranges: 44 maxItems: 1 45 46patternProperties: 47 "-state$": 48 oneOf: 49 - $ref: "#/$defs/qcom-sm8550-lpass-state" 50 - patternProperties: 51 "-pins$": 52 $ref: "#/$defs/qcom-sm8550-lpass-state" 53 additionalProperties: false 54 55$defs: 56 qcom-sm8550-lpass-state: 57 type: object 58 description: 59 Pinctrl node's client devices use subnodes for desired pin configuration. 60 Client device subnodes use below standard properties. 61 $ref: /schemas/pinctrl/pincfg-node.yaml 62 63 properties: 64 pins: 65 description: 66 List of gpio pins affected by the properties specified in this 67 subnode. 68 items: 69 pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" 70 71 function: 72 enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, 73 dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b, 74 ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk, 75 i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, 76 i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk, 77 i2s4_data, i2s4_ws, slimbus_clk, slimbus_data, swr_rx_clk, 78 swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk, 79 wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ] 80 description: 81 Specify the alternative function to be configured for the specified 82 pins. 83 84 drive-strength: 85 enum: [2, 4, 6, 8, 10, 12, 14, 16] 86 default: 2 87 description: 88 Selects the drive strength for the specified pins, in mA. 89 90 slew-rate: 91 enum: [0, 1, 2, 3] 92 default: 0 93 description: | 94 0: No adjustments 95 1: Higher Slew rate (faster edges) 96 2: Lower Slew rate (slower edges) 97 3: Reserved (No adjustments) 98 99 bias-bus-hold: true 100 bias-pull-down: true 101 bias-pull-up: true 102 bias-disable: true 103 input-enable: true 104 output-high: true 105 output-low: true 106 107 required: 108 - pins 109 - function 110 111 additionalProperties: false 112 113allOf: 114 - $ref: pinctrl.yaml# 115 116required: 117 - compatible 118 - reg 119 - clocks 120 - clock-names 121 - gpio-controller 122 - "#gpio-cells" 123 - gpio-ranges 124 125additionalProperties: false 126 127examples: 128 - | 129 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 130 131 lpass_tlmm: pinctrl@6e80000 { 132 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 133 reg = <0x06e80000 0x20000>, 134 <0x0725a000 0x10000>; 135 136 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 137 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 138 clock-names = "core", "audio"; 139 140 gpio-controller; 141 #gpio-cells = <2>; 142 gpio-ranges = <&lpass_tlmm 0 0 23>; 143 144 tx-swr-sleep-clk-state { 145 pins = "gpio0"; 146 function = "swr_tx_clk"; 147 drive-strength = <2>; 148 bias-pull-down; 149 }; 150 }; 151