xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/qcom,sm8450-pinctrl.yaml (revision a90b9d0159070121c221b966469c3e36d912bf82) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SM8450 TLMM block
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description: |
13  This binding describes the Top Level Mode Multiplexer (TLMM) block found
14  in the SM8450 platform.
15
16allOf:
17  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,sm8450-tlmm
22
23  reg:
24    maxItems: 1
25
26  interrupts: true
27  interrupt-controller: true
28  '#interrupt-cells': true
29  gpio-controller: true
30
31  gpio-reserved-ranges:
32    minItems: 1
33    maxItems: 105
34
35  gpio-line-names:
36    maxItems: 209
37
38  '#gpio-cells': true
39  gpio-ranges: true
40  wakeup-parent: true
41
42required:
43  - compatible
44  - reg
45
46additionalProperties: false
47
48patternProperties:
49  '-state$':
50    oneOf:
51      - $ref: "#/$defs/qcom-sm8450-tlmm-state"
52      - patternProperties:
53          "-pins$":
54            $ref: "#/$defs/qcom-sm8450-tlmm-state"
55        additionalProperties: false
56
57$defs:
58  qcom-sm8450-tlmm-state:
59    type: object
60    description:
61      Pinctrl node's client devices use subnodes for desired pin configuration.
62      Client device subnodes use below standard properties.
63
64    properties:
65      pins:
66        description:
67          List of gpio pins affected by the properties specified in this
68          subnode.
69        items:
70          oneOf:
71            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
72            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
73        minItems: 1
74        maxItems: 36
75
76      function:
77        description:
78          Specify the alternative function to be configured for the specified
79          pins.
80        enum: [ aon_cam, atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
81                cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
82                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
83                ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1, gcc_gp2, gcc_gp3,
84                gpio, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1,
85                mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck,
86                mi2s0_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
87                mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
88                mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
89                mss_grfc7, mss_grfc8, mss_grfc9, nav, pcie0_clkreqn,
90                pcie1_clkreqn, phase_flag, pll_bist, pll_clk, pri_mi2s,
91                prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, qlink0_request,
92                qlink0_wmss, qlink1_enable, qlink1_request, qlink1_wmss,
93                qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
94                qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11,
95                qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, qup2,
96                qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4,
97                qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
98                sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
99                tgu_ch3, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
100                tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
101                uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset,
102                usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]
103
104      bias-disable: true
105      bias-pull-down: true
106      bias-pull-up: true
107      drive-strength: true
108      input-enable: true
109      output-high: true
110      output-low: true
111
112    required:
113      - pins
114
115    allOf:
116      - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
117      - if:
118          properties:
119            pins:
120              pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
121        then:
122          required:
123            - function
124
125    additionalProperties: false
126
127examples:
128  - |
129    #include <dt-bindings/interrupt-controller/arm-gic.h>
130    pinctrl@f100000 {
131        compatible = "qcom,sm8450-tlmm";
132        reg = <0x0f100000 0x300000>;
133        gpio-controller;
134        #gpio-cells = <2>;
135        gpio-ranges = <&tlmm 0 0 211>;
136        interrupt-controller;
137        #interrupt-cells = <2>;
138        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
139
140        gpio-wo-state {
141            pins = "gpio1";
142            function = "gpio";
143        };
144
145        uart-w-state {
146            rx-pins {
147                pins = "gpio26";
148                function = "qup7";
149                bias-pull-up;
150            };
151
152            tx-pins {
153                pins = "gpio27";
154                function = "qup7";
155                bias-disable;
156            };
157        };
158    };
159...
160