1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SM8450 SoC LPASS LPI TLMM 8 9maintainers: 10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> 11 12description: 13 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem 14 (LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC. 15 16properties: 17 compatible: 18 const: qcom,sm8450-lpass-lpi-pinctrl 19 20 reg: 21 items: 22 - description: LPASS LPI TLMM Control and Status registers 23 - description: LPASS LPI MCC registers 24 25 clocks: 26 items: 27 - description: LPASS Core voting clock 28 - description: LPASS Audio voting clock 29 30 clock-names: 31 items: 32 - const: core 33 - const: audio 34 35 gpio-controller: true 36 37 "#gpio-cells": 38 description: Specifying the pin number and flags, as defined in 39 include/dt-bindings/gpio/gpio.h 40 const: 2 41 42 gpio-ranges: 43 maxItems: 1 44 45patternProperties: 46 "-state$": 47 oneOf: 48 - $ref: "#/$defs/qcom-sm8450-lpass-state" 49 - patternProperties: 50 "-pins$": 51 $ref: "#/$defs/qcom-sm8450-lpass-state" 52 additionalProperties: false 53 54$defs: 55 qcom-sm8450-lpass-state: 56 type: object 57 description: 58 Pinctrl node's client devices use subnodes for desired pin configuration. 59 Client device subnodes use below standard properties. 60 $ref: /schemas/pinctrl/pincfg-node.yaml 61 62 properties: 63 pins: 64 description: 65 List of gpio pins affected by the properties specified in this 66 subnode. 67 items: 68 pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" 69 70 function: 71 enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data, 72 dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk, 73 dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data, 74 qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws, 75 i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk, 76 wsa2_swr_data, i2s2_data, i2s4_ws, i2s4_clk, i2s4_data, 77 slimbus_clk, i2s3_clk, i2s3_ws, i2s3_data, slimbus_data, 78 ext_mclk1_c, ext_mclk1_b, ext_mclk1_a, ext_mclk1_d, 79 ext_mclk1_e ] 80 description: 81 Specify the alternative function to be configured for the specified 82 pins. 83 84 drive-strength: 85 enum: [2, 4, 6, 8, 10, 12, 14, 16] 86 default: 2 87 description: 88 Selects the drive strength for the specified pins, in mA. 89 90 slew-rate: 91 enum: [0, 1, 2, 3] 92 default: 0 93 description: | 94 0: No adjustments 95 1: Higher Slew rate (faster edges) 96 2: Lower Slew rate (slower edges) 97 3: Reserved (No adjustments) 98 99 bias-bus-hold: true 100 bias-pull-down: true 101 bias-pull-up: true 102 bias-disable: true 103 input-enable: true 104 output-high: true 105 output-low: true 106 107 required: 108 - pins 109 - function 110 111 additionalProperties: false 112 113allOf: 114 - $ref: pinctrl.yaml# 115 116required: 117 - compatible 118 - reg 119 - clocks 120 - clock-names 121 - gpio-controller 122 - "#gpio-cells" 123 - gpio-ranges 124 125additionalProperties: false 126 127examples: 128 - | 129 #include <dt-bindings/sound/qcom,q6afe.h> 130 pinctrl@3440000 { 131 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 132 reg = <0x3440000 0x20000>, 133 <0x34d0000 0x10000>; 134 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 135 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 136 clock-names = "core", "audio"; 137 gpio-controller; 138 #gpio-cells = <2>; 139 gpio-ranges = <&lpi_tlmm 0 0 23>; 140 141 wsa-swr-active-state { 142 clk-pins { 143 pins = "gpio10"; 144 function = "wsa_swr_clk"; 145 drive-strength = <2>; 146 slew-rate = <1>; 147 bias-disable; 148 }; 149 150 data-pins { 151 pins = "gpio11"; 152 function = "wsa_swr_data"; 153 drive-strength = <2>; 154 slew-rate = <1>; 155 }; 156 }; 157 158 tx-swr-sleep-clk-state { 159 pins = "gpio0"; 160 function = "swr_tx_clk"; 161 drive-strength = <2>; 162 bias-pull-down; 163 }; 164 }; 165