xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/qcom,sm8350-pinctrl.yaml (revision e32fecd0c2c3ee37c47ee100f169e7eb0282a873) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SM8350 TLMM block
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description: |
13  This binding describes the Top Level Mode Multiplexer (TLMM) block found
14  in the SM8350 platform.
15
16allOf:
17  - $ref: "pinctrl.yaml#"
18  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
19
20properties:
21  compatible:
22    const: qcom,sm8350-tlmm
23
24  reg:
25    maxItems: 1
26
27  interrupts: true
28  interrupt-controller: true
29  '#interrupt-cells': true
30  gpio-controller: true
31  gpio-reserved-ranges: true
32  '#gpio-cells': true
33  gpio-ranges: true
34  wakeup-parent: true
35
36required:
37  - compatible
38  - reg
39
40additionalProperties: false
41
42patternProperties:
43  '-state$':
44    oneOf:
45      - $ref: "#/$defs/qcom-sm8350-tlmm-state"
46      - patternProperties:
47          ".*":
48            $ref: "#/$defs/qcom-sm8350-tlmm-state"
49
50$defs:
51  qcom-sm8350-tlmm-state:
52    type: object
53    description:
54      Pinctrl node's client devices use subnodes for desired pin configuration.
55      Client device subnodes use below standard properties.
56    $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
57
58    properties:
59      pins:
60        description:
61          List of gpio pins affected by the properties specified in this
62          subnode.
63        items:
64          oneOf:
65            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$"
66            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
67        minItems: 1
68        maxItems: 36
69
70      function:
71        description:
72          Specify the alternative function to be configured for the specified
73          pins.
74
75        enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
76                cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
77                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
78                ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
79                gpio, ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
80                mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
81                mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck,
82                mi2s1_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
83                mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
84                mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
85                mss_grfc7, mss_grfc8, mss_grfc9, nav_gpio, pa_indicator,
86                pcie0_clkreqn, pcie1_clkreqn, phase_flag, pll_bist, pll_clk,
87                pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable,
88                qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
89                qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0,
90                qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10,
91                qup11, qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19,
92                qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5,
93                qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
94                sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
95                tgu_ch3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data,
96                uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present,
97                uim1_reset, usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]
98
99
100      bias-disable: true
101      bias-pull-down: true
102      bias-pull-up: true
103      drive-strength: true
104      input-enable: true
105      output-high: true
106      output-low: true
107
108    required:
109      - pins
110      - function
111
112    additionalProperties: false
113
114examples:
115  - |
116        #include <dt-bindings/interrupt-controller/arm-gic.h>
117        pinctrl@f100000 {
118                compatible = "qcom,sm8350-tlmm";
119                reg = <0x0f100000 0x300000>;
120                interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
121                gpio-controller;
122                #gpio-cells = <2>;
123                interrupt-controller;
124                #interrupt-cells = <2>;
125                gpio-ranges = <&tlmm 0 0 203>;
126
127                gpio-wo-subnode-state {
128                        pins = "gpio1";
129                        function = "gpio";
130                };
131
132                uart-w-subnodes-state {
133                        rx {
134                                pins = "gpio18";
135                                function = "qup3";
136                                bias-pull-up;
137                        };
138
139                        tx {
140                                pins = "gpio19";
141                                function = "qup3";
142                                bias-disable;
143                        };
144                };
145        };
146...
147