1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. SM8250 TLMM block 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 12description: | 13 This binding describes the Top Level Mode Multiplexer block found in the 14 SM8250 platform. 15 16properties: 17 compatible: 18 const: qcom,sm8250-pinctrl 19 20 reg: 21 minItems: 3 22 maxItems: 3 23 24 reg-names: 25 items: 26 - const: "west" 27 - const: "south" 28 - const: "north" 29 30 interrupts: 31 description: Specifies the TLMM summary IRQ 32 maxItems: 1 33 34 interrupt-controller: true 35 36 '#interrupt-cells': 37 description: 38 Specifies the PIN numbers and Flags, as defined in defined in 39 include/dt-bindings/interrupt-controller/irq.h 40 const: 2 41 42 gpio-controller: true 43 44 '#gpio-cells': 45 description: Specifying the pin number and flags, as defined in 46 include/dt-bindings/gpio/gpio.h 47 const: 2 48 49 gpio-ranges: 50 maxItems: 1 51 52 wakeup-parent: 53 maxItems: 1 54 55#PIN CONFIGURATION NODES 56patternProperties: 57 '^.*$': 58 if: 59 type: object 60 then: 61 properties: 62 pins: 63 description: 64 List of gpio pins affected by the properties specified in this 65 subnode. 66 items: 67 oneOf: 68 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" 69 - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] 70 minItems: 1 71 maxItems: 36 72 73 function: 74 description: 75 Specify the alternative function to be configured for the specified 76 pins. 77 78 enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c, 79 cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng, 80 cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, 81 ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio, 82 ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, 83 mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, 84 mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, 85 mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1, 86 pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset, 87 pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3, 88 qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14, 89 qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6, 90 qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41, 91 sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1, 92 tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data, 93 tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en, 94 tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ] 95 96 drive-strength: 97 enum: [2, 4, 6, 8, 10, 12, 14, 16] 98 default: 2 99 description: 100 Selects the drive strength for the specified pins, in mA. 101 102 bias-pull-down: true 103 104 bias-pull-up: true 105 106 bias-disable: true 107 108 output-high: true 109 110 output-low: true 111 112 required: 113 - pins 114 - function 115 116 additionalProperties: false 117 118required: 119 - compatible 120 - reg 121 - reg-names 122 - interrupts 123 - interrupt-controller 124 - '#interrupt-cells' 125 - gpio-controller 126 - '#gpio-cells' 127 - gpio-ranges 128 129additionalProperties: false 130 131examples: 132 - | 133 #include <dt-bindings/interrupt-controller/arm-gic.h> 134 pinctrl@1f00000 { 135 compatible = "qcom,sm8250-pinctrl"; 136 reg = <0x0f100000 0x300000>, 137 <0x0f500000 0x300000>, 138 <0x0f900000 0x300000>; 139 reg-names = "west", "south", "north"; 140 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 141 gpio-controller; 142 #gpio-cells = <2>; 143 interrupt-controller; 144 #interrupt-cells = <2>; 145 gpio-ranges = <&tlmm 0 0 180>; 146 wakeup-parent = <&pdc>; 147 }; 148