xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/qcom,sm8150-pinctrl.yaml (revision a0ca4af9455b844c5e094fc1b09b1390ffa979fc) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8150-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8150 TLMM pin controller
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12
13description:
14  Top Level Mode Multiplexer pin controller in Qualcomm SM8150 SoC.
15
16properties:
17  compatible:
18    const: qcom,sm8150-pinctrl
19
20  reg:
21    maxItems: 4
22
23  reg-names:
24    items:
25      - const: west
26      - const: east
27      - const: north
28      - const: south
29
30  interrupts:
31    maxItems: 1
32
33  gpio-reserved-ranges:
34    minItems: 1
35    maxItems: 88
36
37  gpio-line-names:
38    maxItems: 175
39
40patternProperties:
41  "-state$":
42    oneOf:
43      - $ref: "#/$defs/qcom-sm8150-tlmm-state"
44      - patternProperties:
45          "-pins$":
46            $ref: "#/$defs/qcom-sm8150-tlmm-state"
47        additionalProperties: false
48
49$defs:
50  qcom-sm8150-tlmm-state:
51    type: object
52    description:
53      Pinctrl node's client devices use subnodes for desired pin configuration.
54      Client device subnodes use below standard properties.
55    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
56    unevaluatedProperties: false
57
58    properties:
59      pins:
60        description:
61          List of gpio pins affected by the properties specified in this
62          subnode.
63        items:
64          oneOf:
65            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
66            - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
67        minItems: 1
68        maxItems: 36
69
70      function:
71        description:
72          Specify the alternative function to be configured for the specified
73          pins.
74
75        enum: [ adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
76                atest_char0, atest_char1, atest_char2, atest_char3, audio_ref,
77                atest_usb1, atest_usb2, atest_usb10, atest_usb11, atest_usb12,
78                atest_usb13, atest_usb20, atest_usb21, atest_usb22,
79                atest_usb23, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
80                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
81                cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
82                ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd, emac_phy, emac_pps,
83                gcc_gp1, gcc_gp2, gcc_gp3, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s,
84                jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
85                mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator,
86                pci_e0, phase_flag, pll_bypassnl, pll_bist, pci_e1, pll_reset,
87                pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti,
88                qlink_request, qlink_enable, qspi0, qspi1, qspi2, qspi3,
89                qspi_clk, qspi_cs, qua_mi2s, qup0, qup1, qup2, qup3, qup4,
90                qup5, qup6, qup7, qup8, qup9, qup10, qup11, qup12, qup13,
91                qup14, qup15, qup16, qup17, qup18, qup19, qup_l4, qup_l5,
92                qup_l6, rgmii, sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu,
93                ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
94                tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, usb2phy_ac,
95                usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
96                wlan2_adc0, wlan2_adc1, wmss_reset ]
97
98    required:
99      - pins
100
101allOf:
102  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
103
104required:
105  - compatible
106  - reg
107  - reg-names
108
109unevaluatedProperties: false
110
111examples:
112  - |
113    #include <dt-bindings/interrupt-controller/arm-gic.h>
114
115    tlmm: pinctrl@3100000 {
116        compatible = "qcom,sm8150-pinctrl";
117        reg = <0x03100000 0x300000>,
118              <0x03500000 0x300000>,
119              <0x03900000 0x300000>,
120              <0x03d00000 0x300000>;
121        reg-names = "west", "east", "north", "south";
122        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
123        gpio-ranges = <&tlmm 0 0 176>;
124        gpio-controller;
125        #gpio-cells = <2>;
126        interrupt-controller;
127        #interrupt-cells = <2>;
128        wakeup-parent = <&pdc>;
129
130        qup-spi0-default-state {
131            pins = "gpio0", "gpio1", "gpio2", "gpio3";
132            function = "qup0";
133            drive-strength = <6>;
134            bias-disable;
135        };
136
137        pcie1-default-state {
138            perst-pins {
139                pins = "gpio102";
140                function = "gpio";
141                drive-strength = <2>;
142                bias-pull-down;
143            };
144
145            clkreq-pins {
146                pins = "gpio103";
147                function = "pci_e1";
148                drive-strength = <2>;
149                bias-pull-up;
150            };
151
152            wake-pins {
153                pins = "gpio104";
154                function = "gpio";
155                drive-strength = <2>;
156                bias-pull-up;
157            };
158        };
159    };
160