1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sm6375-tlmm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. SM6375 TLMM block 8 9maintainers: 10 - Konrad Dybcio <konrad.dybcio@somainline.org> 11 12description: 13 Top Level Mode Multiplexer pin controller in Qualcomm SM6375 SoC. 14 15allOf: 16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 17 18properties: 19 compatible: 20 const: qcom,sm6375-tlmm 21 22 reg: 23 maxItems: 1 24 25 interrupts: true 26 interrupt-controller: true 27 "#interrupt-cells": true 28 gpio-controller: true 29 gpio-reserved-ranges: true 30 "#gpio-cells": true 31 gpio-ranges: true 32 wakeup-parent: true 33 34required: 35 - compatible 36 - reg 37 38additionalProperties: false 39 40patternProperties: 41 "-state$": 42 oneOf: 43 - $ref: "#/$defs/qcom-sm6375-tlmm-state" 44 - patternProperties: 45 "-pins$": 46 $ref: "#/$defs/qcom-sm6375-tlmm-state" 47 additionalProperties: false 48 49$defs: 50 qcom-sm6375-tlmm-state: 51 type: object 52 description: 53 Pinctrl node's client devices use subnodes for desired pin configuration. 54 Client device subnodes use below standard properties. 55 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 56 57 properties: 58 pins: 59 description: 60 List of gpio pins affected by the properties specified in this 61 subnode. 62 items: 63 oneOf: 64 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-6])$" 65 - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, 66 sdc2_cmd, sdc2_data ] 67 minItems: 1 68 maxItems: 36 69 70 function: 71 description: 72 Specify the alternative function to be configured for the specified 73 pins. 74 75 enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, 76 atest_char2, atest_char3, atest_tsens, atest_tsens2, 77 atest_usb1, atest_usb10, atest_usb11, atest_usb12, 78 atest_usb13, atest_usb2, atest_usb20, atest_usb21, 79 atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk, 80 cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, 81 cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist, 82 ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, 83 gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio, 84 gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext, 85 m_voc, mclk, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, 86 mdp_vsync3, mi2s_0, mi2s_1, mi2s_2, mss_lte, nav_gpio, 87 nav_pps, pa_indicator, phase_flag0, phase_flag1, phase_flag10, 88 phase_flag11, phase_flag12, phase_flag13, phase_flag14, 89 phase_flag15, phase_flag16, phase_flag17, phase_flag18, 90 phase_flag19, phase_flag2, phase_flag20, phase_flag21, 91 phase_flag22, phase_flag23, phase_flag24, phase_flag25, 92 phase_flag26, phase_flag27, phase_flag28, phase_flag29, 93 phase_flag3, phase_flag30, phase_flag31, phase_flag4, 94 phase_flag5, phase_flag6, phase_flag7, phase_flag8, 95 phase_flag9, pll_bist, pll_bypassnl, pll_clk, pll_reset, 96 prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, 97 qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11, 98 qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15, 99 qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, 100 qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable, 101 qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request, 102 qlink1_wmss, qup00, qup01, qup02, qup10, qup11_f1, qup11_f2, 103 qup12, qup13_f1, qup13_f2, qup14, sd_write, sdc1_tb, sdc2_tb, 104 sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, 105 tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset, 106 uim2_clk, uim2_data, uim2_present, uim2_reset, usb2phy_ac, 107 usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, 108 wlan2_adc0, wlan2_adc1 ] 109 110 111 bias-disable: true 112 bias-pull-down: true 113 bias-pull-up: true 114 drive-strength: true 115 input-enable: true 116 output-high: true 117 output-low: true 118 119 required: 120 - pins 121 122 additionalProperties: false 123 124examples: 125 - | 126 #include <dt-bindings/interrupt-controller/arm-gic.h> 127 pinctrl@500000 { 128 compatible = "qcom,sm6375-tlmm"; 129 reg = <0x00500000 0x800000>; 130 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 131 gpio-controller; 132 #gpio-cells = <2>; 133 interrupt-controller; 134 #interrupt-cells = <2>; 135 gpio-ranges = <&tlmm 0 0 157>; 136 137 gpio-wo-subnode-state { 138 pins = "gpio1"; 139 function = "gpio"; 140 }; 141 142 uart-w-subnodes-state { 143 rx-pins { 144 pins = "gpio18"; 145 function = "qup13_f2"; 146 bias-pull-up; 147 }; 148 149 tx-pins { 150 pins = "gpio19"; 151 function = "qup13_f2"; 152 bias-disable; 153 }; 154 }; 155 }; 156... 157