xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/qcom,sm6375-tlmm.yaml (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm6375-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SM6375 TLMM block
8
9maintainers:
10  - Konrad Dybcio <konrad.dybcio@somainline.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm SM6375 SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm6375-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  interrupt-controller: true
29  "#interrupt-cells": true
30  gpio-controller: true
31  gpio-reserved-ranges: true
32  "#gpio-cells": true
33  gpio-ranges: true
34  wakeup-parent: true
35
36required:
37  - compatible
38  - reg
39
40additionalProperties: false
41
42patternProperties:
43  "-state$":
44    oneOf:
45      - $ref: "#/$defs/qcom-sm6375-tlmm-state"
46      - patternProperties:
47          "-pins$":
48            $ref: "#/$defs/qcom-sm6375-tlmm-state"
49        additionalProperties: false
50
51$defs:
52  qcom-sm6375-tlmm-state:
53    type: object
54    description:
55      Pinctrl node's client devices use subnodes for desired pin configuration.
56      Client device subnodes use below standard properties.
57    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
58    unevaluatedProperties: false
59
60    properties:
61      pins:
62        description:
63          List of gpio pins affected by the properties specified in this
64          subnode.
65        items:
66          oneOf:
67            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$"
68            - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
69                      sdc2_cmd, sdc2_data ]
70        minItems: 1
71        maxItems: 36
72
73      function:
74        description:
75          Specify the alternative function to be configured for the specified
76          pins.
77
78        enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
79                atest_char2, atest_char3, atest_tsens, atest_tsens2,
80                atest_usb1, atest_usb10, atest_usb11, atest_usb12,
81                atest_usb13, atest_usb2, atest_usb20, atest_usb21,
82                atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
83                cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
84                cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist,
85                ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd,
86                gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio,
87                gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext,
88                m_voc, mclk, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
89                mdp_vsync3, mi2s_0, mi2s_1, mi2s_2, mss_lte, nav_gpio,
90                nav_pps, pa_indicator, phase_flag0, phase_flag1, phase_flag10,
91                phase_flag11, phase_flag12, phase_flag13, phase_flag14,
92                phase_flag15, phase_flag16, phase_flag17, phase_flag18,
93                phase_flag19, phase_flag2, phase_flag20, phase_flag21,
94                phase_flag22, phase_flag23, phase_flag24, phase_flag25,
95                phase_flag26, phase_flag27, phase_flag28, phase_flag29,
96                phase_flag3, phase_flag30, phase_flag31, phase_flag4,
97                phase_flag5, phase_flag6, phase_flag7, phase_flag8,
98                phase_flag9, pll_bist, pll_bypassnl, pll_clk, pll_reset,
99                prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
100                qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11,
101                qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15,
102                qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6,
103                qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable,
104                qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
105                qlink1_wmss, qup00, qup01, qup02, qup10, qup11_f1, qup11_f2,
106                qup12, qup13_f1, qup13_f2, qup14, sd_write, sdc1_tb, sdc2_tb,
107                sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
108                tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset,
109                uim2_clk, uim2_data, uim2_present, uim2_reset, usb2phy_ac,
110                usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
111                wlan2_adc0, wlan2_adc1 ]
112
113    required:
114      - pins
115
116examples:
117  - |
118    #include <dt-bindings/interrupt-controller/arm-gic.h>
119    pinctrl@500000 {
120        compatible = "qcom,sm6375-tlmm";
121        reg = <0x00500000 0x800000>;
122        interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
123        gpio-controller;
124        #gpio-cells = <2>;
125        interrupt-controller;
126        #interrupt-cells = <2>;
127        gpio-ranges = <&tlmm 0 0 157>; /* GPIOs + ufs_reset */
128
129        gpio-wo-subnode-state {
130            pins = "gpio1";
131            function = "gpio";
132        };
133
134        uart-w-subnodes-state {
135            rx-pins {
136                pins = "gpio18";
137                function = "qup13_f2";
138                bias-pull-up;
139            };
140
141            tx-pins {
142                pins = "gpio19";
143                function = "qup13_f2";
144                bias-disable;
145            };
146        };
147    };
148...
149