xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/qcom,sm6350-tlmm.yaml (revision aa1a8ff2d6dbc51ef058f46f3db5a8bb77967145) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SM6350 TLMM block
8
9maintainers:
10  - Konrad Dybcio <konrad.dybcio@somainline.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm SM6350 SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm6350-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    minItems: 9
27    maxItems: 9
28
29  interrupt-controller: true
30  "#interrupt-cells": true
31  gpio-controller: true
32
33  gpio-reserved-ranges:
34    minItems: 1
35    maxItems: 78
36
37  gpio-line-names:
38    maxItems: 156
39
40  "#gpio-cells": true
41  gpio-ranges: true
42  wakeup-parent: true
43
44required:
45  - compatible
46  - reg
47
48additionalProperties: false
49
50patternProperties:
51  "-state$":
52    oneOf:
53      - $ref: "#/$defs/qcom-sm6350-tlmm-state"
54      - patternProperties:
55          "-pins$":
56            $ref: "#/$defs/qcom-sm6350-tlmm-state"
57        additionalProperties: false
58
59$defs:
60  qcom-sm6350-tlmm-state:
61    type: object
62    description:
63      Pinctrl node's client devices use subnodes for desired pin configuration.
64      Client device subnodes use below standard properties.
65    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
66    unevaluatedProperties: false
67
68    properties:
69      pins:
70        description:
71          List of gpio pins affected by the properties specified in this
72          subnode.
73        items:
74          oneOf:
75            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$"
76            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
77        minItems: 1
78        maxItems: 36
79
80      function:
81        description:
82          Specify the alternative function to be configured for the specified
83          pins.
84
85        enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, atest_char2,
86                atest_char3, atest_tsens, atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
87                atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21, atest_usb22,
88                atest_usb23, audio_ref, btfm_slimbus, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3,
89                cam_mclk4, cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
90                cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3,
91                dp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio,
92                gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext, m_voc, mclk,
93                mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1, mi2s_2,
94                mss_lte, nav_gpio, nav_pps, pa_indicator, pcie0_clk, phase_flag0, phase_flag1,
95                phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15,
96                phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20,
97                phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26,
98                phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31,
99                phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9,
100                pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti, qdss_gpio, qdss_gpio0,
101                qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
102                qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6,
103                qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable, qlink0_request, qlink0_wmss,
104                qlink1_enable, qlink1_request, qlink1_wmss, qup00, qup01, qup02, qup10, qup11,
105                qup12, qup13_f1, qup13_f2, qup14, rffe0_clk, rffe0_data, rffe1_clk, rffe1_data,
106                rffe2_clk, rffe2_data, rffe3_clk, rffe3_data, rffe4_clk, rffe4_data, sd_write,
107                sdc1_tb, sdc2_tb, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
108                tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
109                uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
110                wlan2_adc0, wlan2_adc1, ]
111
112    required:
113      - pins
114
115examples:
116  - |
117    #include <dt-bindings/interrupt-controller/arm-gic.h>
118    pinctrl@f100000 {
119        compatible = "qcom,sm6350-tlmm";
120        reg = <0x0f100000 0x300000>;
121        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
122                     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
123                     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
124                     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
125                     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
126                     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
127                     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
128                     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
129                     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
130
131        gpio-controller;
132        #gpio-cells = <2>;
133        interrupt-controller;
134        #interrupt-cells = <2>;
135        gpio-ranges = <&tlmm 0 0 157>;
136
137        gpio-wo-subnode-state {
138            pins = "gpio1";
139            function = "gpio";
140        };
141
142        uart-w-subnodes-state {
143            rx-pins {
144                pins = "gpio25";
145                function = "qup13_f2";
146                bias-disable;
147            };
148
149            tx-pins {
150                pins = "gpio26";
151                function = "qup13_f2";
152                bias-disable;
153            };
154        };
155    };
156...
157