xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/qcom,sm6125-tlmm.yaml (revision 95eb4b873b6a8b527c5bd78d7191975dfca38998) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6title: Qualcomm Technologies, Inc. SM6125 TLMM block
7
8maintainers:
9  - Martin Botka <martin.botka@somainline.org>
10
11description:
12  Top Level Mode Multiplexer pin controller in Qualcomm SM6125 SoC.
13
14allOf:
15  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
16
17properties:
18  compatible:
19    const: qcom,sm6125-tlmm
20
21  reg:
22    maxItems: 3
23
24  reg-names:
25    items:
26      - const: west
27      - const: south
28      - const: east
29
30  interrupts:
31    maxItems: 1
32
33  gpio-reserved-ranges: true
34
35patternProperties:
36  "-state$":
37    oneOf:
38      - $ref: "#/$defs/qcom-sm6125-tlmm-state"
39      - patternProperties:
40          "-pins$":
41            $ref: "#/$defs/qcom-sm6125-tlmm-state"
42        additionalProperties: false
43
44$defs:
45  qcom-sm6125-tlmm-state:
46    type: object
47    description:
48      Pinctrl node's client devices use subnodes for desired pin configuration.
49      Client device subnodes use below standard properties.
50    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51    unevaluatedProperties: false
52
53    properties:
54      pins:
55        description:
56          List of gpio pins affected by the properties specified in this
57          subnode.
58        items:
59          oneOf:
60            - pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$"
61            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
62        minItems: 1
63        maxItems: 36
64
65      function:
66        description:
67          Specify the alternative function to be configured for the specified
68          pins.
69
70        enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
71                atest_char2, atest_char3, atest_tsens, atest_tsens2, atest_usb1,
72                atest_usb10, atest_usb11, atest_usb12, atest_usb13, atest_usb2,
73                atest_usb20, atest_usb21, atest_usb22, atest_usb23, aud_sb,
74                audio_ref, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
75                cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, cri_trng,
76                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
77                ddr_pxi2, ddr_pxi3, debug_hot, dmic0_clk, dmic0_data, dmic1_clk,
78                dmic1_data, dp_hot, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
79                gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en,
80                ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0, mdp_vsync1,
81                mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, mpm_pwr, mss_lte,
82                nav_pps, pa_indicator, phase_flag, pll_bist, pll_bypassnl, pll_reset,
83                pri_mi2s, pri_mi2s_ws, prng_rosc, qca_sb, qdss_cti, qdss, qlink_enable,
84                qlink_request, qua_mi2s, qui_mi2s, qup00, qup01, qup02, qup03, qup04,
85                qup10, qup11, qup12, qup13, qup14, sd_write, sec_mi2s, sp_cmu, swr_rx,
86                swr_tx, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm,
87                uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
88                uim2_present, uim2_reset, unused1, unused2, usb_phy, vfr_1, vsense_trigger,
89                wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data ]
90
91
92    required:
93      - pins
94
95required:
96  - compatible
97  - reg
98  - reg-names
99
100unevaluatedProperties: false
101
102examples:
103  - |
104    #include <dt-bindings/interrupt-controller/arm-gic.h>
105    pinctrl@500000 {
106        compatible = "qcom,sm6125-tlmm";
107        reg = <0x00500000 0x400000>,
108              <0x00900000 0x400000>,
109              <0x00d00000 0x400000>;
110        reg-names = "west", "south", "east";
111        interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
112        gpio-controller;
113        gpio-ranges = <&tlmm 0 0 134>;
114        #gpio-cells = <2>;
115        interrupt-controller;
116        #interrupt-cells = <2>;
117
118        sdc2-off-state {
119            clk-pins {
120                pins = "sdc2_clk";
121                drive-strength = <2>;
122                bias-disable;
123            };
124
125            cmd-pins {
126                pins = "sdc2_cmd";
127                drive-strength = <2>;
128                bias-pull-up;
129            };
130
131            data-pins {
132                pins = "sdc2_data";
133                drive-strength = <2>;
134                bias-pull-up;
135            };
136        };
137    };
138