xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/qcom,sm6125-pinctrl.yaml (revision 7ef62cebc2f965b0f640263e179276928885e33d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6title: Qualcomm Technologies, Inc. SM6125 TLMM block
7
8maintainers:
9  - Martin Botka <martin.botka@somainline.org>
10
11description: |
12  This binding describes the Top Level Mode Multiplexer (TLMM) block found
13  in the SM6125 platform.
14
15allOf:
16  - $ref: "pinctrl.yaml#"
17  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,sm6125-tlmm
22
23  reg:
24    minItems: 3
25    maxItems: 3
26
27  reg-names:
28    items:
29      - const: "west"
30      - const: "south"
31      - const: "east"
32
33  interrupts: true
34  interrupt-controller: true
35  '#interrupt-cells': true
36  gpio-controller: true
37  gpio-reserved-ranges: true
38  '#gpio-cells': true
39  gpio-ranges: true
40  wakeup-parent: true
41
42required:
43  - compatible
44  - reg
45  - reg-names
46
47additionalProperties: false
48
49patternProperties:
50  '-state$':
51    oneOf:
52      - $ref: "#/$defs/qcom-sm6125-tlmm-state"
53      - patternProperties:
54          "-pins$":
55            $ref: "#/$defs/qcom-sm6125-tlmm-state"
56        additionalProperties: false
57
58$defs:
59  qcom-sm6125-tlmm-state:
60    type: object
61    description:
62      Pinctrl node's client devices use subnodes for desired pin configuration.
63      Client device subnodes use below standard properties.
64
65    properties:
66      pins:
67        description:
68          List of gpio pins affected by the properties specified in this
69          subnode.
70        items:
71          oneOf:
72            - pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$"
73            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
74        minItems: 1
75        maxItems: 36
76
77      function:
78        description:
79          Specify the alternative function to be configured for the specified
80          pins.
81
82        enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
83                atest_char2, atest_char3, atest_tsens, atest_tsens2, atest_usb1,
84                atest_usb10, atest_usb11, atest_usb12, atest_usb13, atest_usb2,
85                atest_usb20, atest_usb21, atest_usb22, atest_usb23, aud_sb,
86                audio_ref, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
87                cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, cri_trng,
88                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
89                ddr_pxi2, ddr_pxi3, debug_hot, dmic0_clk, dmic0_data, dmic1_clk,
90                dmic1_data, dp_hot, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
91                gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en,
92                ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0, mdp_vsync1,
93                mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, mpm_pwr, mss_lte,
94                nav_pps, pa_indicator, phase_flag, pll_bist, pll_bypassnl, pll_reset,
95                pri_mi2s, pri_mi2s_ws, prng_rosc, qca_sb, qdss_cti, qdss, qlink_enable,
96                qlink_request, qua_mi2s, qui_mi2s, qup00, qup01, qup02, qup03, qup04,
97                qup10, qup11, qup12, qup13, qup14, sd_write, sec_mi2s, sp_cmu, swr_rx,
98                swr_tx, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm,
99                uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
100                uim2_present, uim2_reset, unused1, unused2, usb_phy, vfr_1, vsense_trigger,
101                wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data ]
102
103
104      bias-disable: true
105      bias-pull-down: true
106      bias-pull-up: true
107      drive-strength: true
108      input-enable: true
109      output-high: true
110      output-low: true
111
112    required:
113      - pins
114
115    allOf:
116      - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
117      - if:
118          properties:
119            pins:
120              pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$"
121        then:
122          required:
123            - function
124
125    additionalProperties: false
126
127examples:
128  - |
129    #include <dt-bindings/interrupt-controller/arm-gic.h>
130    pinctrl@500000 {
131        compatible = "qcom,sm6125-tlmm";
132        reg = <0x00500000 0x400000>,
133              <0x00900000 0x400000>,
134              <0x00d00000 0x400000>;
135        reg-names = "west", "south", "east";
136        interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
137        gpio-controller;
138        gpio-ranges = <&tlmm 0 0 134>;
139        #gpio-cells = <2>;
140        interrupt-controller;
141        #interrupt-cells = <2>;
142
143        sdc2-off-state {
144            clk-pins {
145                pins = "sdc2_clk";
146                drive-strength = <2>;
147                bias-disable;
148            };
149
150            cmd-pins {
151                pins = "sdc2_cmd";
152                drive-strength = <2>;
153                bias-pull-up;
154            };
155
156            data-pins {
157                pins = "sdc2_data";
158                drive-strength = <2>;
159                bias-pull-up;
160            };
161        };
162    };
163