1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6title: Qualcomm Technologies, Inc. SM6125 TLMM block 7 8maintainers: 9 - Martin Botka <martin.botka@somainline.org> 10 11description: | 12 This binding describes the Top Level Mode Multiplexer (TLMM) block found 13 in the SM6125 platform. 14 15allOf: 16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 17 18properties: 19 compatible: 20 const: qcom,sm6125-tlmm 21 22 reg: 23 minItems: 3 24 maxItems: 3 25 26 reg-names: 27 items: 28 - const: "west" 29 - const: "south" 30 - const: "east" 31 32 interrupts: true 33 interrupt-controller: true 34 '#interrupt-cells': true 35 gpio-controller: true 36 gpio-reserved-ranges: true 37 '#gpio-cells': true 38 gpio-ranges: true 39 wakeup-parent: true 40 41required: 42 - compatible 43 - reg 44 - reg-names 45 46additionalProperties: false 47 48patternProperties: 49 '-state$': 50 oneOf: 51 - $ref: "#/$defs/qcom-sm6125-tlmm-state" 52 - patternProperties: 53 ".*": 54 $ref: "#/$defs/qcom-sm6125-tlmm-state" 55 56$defs: 57 qcom-sm6125-tlmm-state: 58 type: object 59 description: 60 Pinctrl node's client devices use subnodes for desired pin configuration. 61 Client device subnodes use below standard properties. 62 $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" 63 64 properties: 65 pins: 66 description: 67 List of gpio pins affected by the properties specified in this 68 subnode. 69 items: 70 oneOf: 71 - pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$" 72 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] 73 minItems: 1 74 maxItems: 36 75 76 function: 77 description: 78 Specify the alternative function to be configured for the specified 79 pins. 80 81 enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, 82 atest_char2, atest_char3, atest_tsens, atest_tsens2, atest_usb1, 83 atest_usb10, atest_usb11, atest_usb12, atest_usb13, atest_usb2, 84 atest_usb20, atest_usb21, atest_usb22, atest_usb23, aud_sb, 85 audio_ref, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1, 86 cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, cri_trng, 87 cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, 88 ddr_pxi2, ddr_pxi3, debug_hot, dmic0_clk, dmic0_data, dmic1_clk, 89 dmic1_data, dp_hot, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, 90 gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en, 91 ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0, mdp_vsync1, 92 mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, mpm_pwr, mss_lte, 93 nav_pps, pa_indicator, phase_flag, pll_bist, pll_bypassnl, pll_reset, 94 pri_mi2s, pri_mi2s_ws, prng_rosc, qca_sb, qdss_cti, qdss, qlink_enable, 95 qlink_request, qua_mi2s, qui_mi2s, qup00, qup01, qup02, qup03, qup04, 96 qup10, qup11, qup12, qup13, qup14, sd_write, sec_mi2s, sp_cmu, swr_rx, 97 swr_tx, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm, 98 uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, 99 uim2_present, uim2_reset, unused1, unused2, usb_phy, vfr_1, vsense_trigger, 100 wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data ] 101 102 103 bias-disable: true 104 bias-pull-down: true 105 bias-pull-up: true 106 drive-strength: true 107 input-enable: true 108 output-high: true 109 output-low: true 110 111 required: 112 - pins 113 - function 114 115 additionalProperties: false 116 117examples: 118 - | 119 #include <dt-bindings/interrupt-controller/arm-gic.h> 120 pinctrl@500000 { 121 compatible = "qcom,sm6125-tlmm"; 122 reg = <0x00500000 0x400000>, 123 <0x00900000 0x400000>, 124 <0x00d00000 0x400000>; 125 reg-names = "west", "south", "east"; 126 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 127 gpio-controller; 128 gpio-ranges = <&tlmm 0 0 134>; 129 #gpio-cells = <2>; 130 interrupt-controller; 131 #interrupt-cells = <2>; 132 }; 133