1Qualcomm SDM845 TLMM block 2 3This binding describes the Top Level Mode Multiplexer block found in the 4SDM845 platform. 5 6- compatible: 7 Usage: required 8 Value type: <string> 9 Definition: must be "qcom,sdm845-pinctrl" 10 11- reg: 12 Usage: required 13 Value type: <prop-encoded-array> 14 Definition: the base address and size of the TLMM register space. 15 16- interrupts: 17 Usage: required 18 Value type: <prop-encoded-array> 19 Definition: should specify the TLMM summary IRQ. 20 21- interrupt-controller: 22 Usage: required 23 Value type: <none> 24 Definition: identifies this node as an interrupt controller 25 26- #interrupt-cells: 27 Usage: required 28 Value type: <u32> 29 Definition: must be 2. Specifying the pin number and flags, as defined 30 in <dt-bindings/interrupt-controller/irq.h> 31 32- gpio-controller: 33 Usage: required 34 Value type: <none> 35 Definition: identifies this node as a gpio controller 36 37- #gpio-cells: 38 Usage: required 39 Value type: <u32> 40 Definition: must be 2. Specifying the pin number and flags, as defined 41 in <dt-bindings/gpio/gpio.h> 42 43Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for 44a general description of GPIO and interrupt bindings. 45 46Please refer to pinctrl-bindings.txt in this directory for details of the 47common pinctrl bindings used by client devices, including the meaning of the 48phrase "pin configuration node". 49 50The pin configuration nodes act as a container for an arbitrary number of 51subnodes. Each of these subnodes represents some desired configuration for a 52pin, a group, or a list of pins or groups. This configuration can include the 53mux function to select on those pin(s)/group(s), and various pin configuration 54parameters, such as pull-up, drive strength, etc. 55 56 57PIN CONFIGURATION NODES: 58 59The name of each subnode is not important; all subnodes should be enumerated 60and processed purely based on their content. 61 62Each subnode only affects those parameters that are explicitly listed. In 63other words, a subnode that lists a mux function but no pin configuration 64parameters implies no information about any pin configuration parameters. 65Similarly, a pin subnode that describes a pullup parameter implies no 66information about e.g. the mux function. 67 68 69The following generic properties as defined in pinctrl-bindings.txt are valid 70to specify in a pin configuration subnode: 71 72- pins: 73 Usage: required 74 Value type: <string-array> 75 Definition: List of gpio pins affected by the properties specified in 76 this subnode. 77 78 Valid pins are: 79 gpio0-gpio149 80 Supports mux, bias and drive-strength 81 82 sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset 83 Supports bias and drive-strength 84 85- function: 86 Usage: required 87 Value type: <string> 88 Definition: Specify the alternative function to be configured for the 89 specified pins. Functions are only valid for gpio pins. 90 Valid values are: 91 92 gpio, adsp_ext, agera_pll, atest_char, atest_tsens, 93 atest_tsens2, atest_usb1, atest_usb10, atest_usb11, 94 atest_usb12, atest_usb13, atest_usb2, atest_usb20, 95 atest_usb21, atest_usb22, atest_usb23, audio_ref, 96 btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0, 97 cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng, 98 cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, 99 ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, 100 gcc_gp2, gcc_gp3, jitter_bist, ldo_en, ldo_update, 101 lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, 102 mdp_vsync2, mdp_vsync3, mss_lte, nav_pps, pa_indicator, 103 pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl, 104 pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, 105 qdss, qlink_enable, qlink_request, qua_mi2s, qup0, qup1, 106 qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3, qup4, 107 qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, 108 qspi_clk, qspi_cs, qspi_data, sd_write, sdc4_clk, sdc4_cmd, 109 sdc4_data, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu_ch0, 110 tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, 111 tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, 112 tsif2_clk, tsif2_data, tsif2_en, tsif2_error, tsif2_sync, 113 uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, 114 uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, 115 vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, 116 wlan2_adc1, 117 118- bias-disable: 119 Usage: optional 120 Value type: <none> 121 Definition: The specified pins should be configured as no pull. 122 123- bias-pull-down: 124 Usage: optional 125 Value type: <none> 126 Definition: The specified pins should be configured as pull down. 127 128- bias-pull-up: 129 Usage: optional 130 Value type: <none> 131 Definition: The specified pins should be configured as pull up. 132 133- output-high: 134 Usage: optional 135 Value type: <none> 136 Definition: The specified pins are configured in output mode, driven 137 high. 138 Not valid for sdc pins. 139 140- output-low: 141 Usage: optional 142 Value type: <none> 143 Definition: The specified pins are configured in output mode, driven 144 low. 145 Not valid for sdc pins. 146 147- drive-strength: 148 Usage: optional 149 Value type: <u32> 150 Definition: Selects the drive strength for the specified pins, in mA. 151 Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 152 153Example: 154 155 tlmm: pinctrl@3400000 { 156 compatible = "qcom,sdm845-pinctrl"; 157 reg = <0x03400000 0xc00000>; 158 interrupts = <GIC_SPI 208 0>; 159 gpio-controller; 160 #gpio-cells = <2>; 161 interrupt-controller; 162 #interrupt-cells = <2>; 163 164 qup9_active: qup9-active { 165 mux { 166 pins = "gpio4", "gpio5"; 167 function = "qup9"; 168 }; 169 170 config { 171 pins = "gpio4", "gpio5"; 172 drive-strength = <2>; 173 bias-disable; 174 }; 175 }; 176 }; 177