1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-tlmm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Technologies, Inc. SC8280XP TLMM block 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 12description: | 13 Top Level Mode Multiplexer pin controller in Qualcomm SC8280XP SoC. 14 15allOf: 16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# 17 18properties: 19 compatible: 20 const: qcom,sc8280xp-tlmm 21 22 reg: 23 maxItems: 1 24 25 interrupts: true 26 interrupt-controller: true 27 "#interrupt-cells": true 28 gpio-controller: true 29 gpio-reserved-ranges: true 30 "#gpio-cells": true 31 gpio-ranges: true 32 wakeup-parent: true 33 34required: 35 - compatible 36 - reg 37 38additionalProperties: false 39 40patternProperties: 41 "-state$": 42 oneOf: 43 - $ref: "#/$defs/qcom-sc8280xp-tlmm-state" 44 - patternProperties: 45 "-pins$": 46 $ref: "#/$defs/qcom-sc8280xp-tlmm-state" 47 additionalProperties: false 48 49$defs: 50 qcom-sc8280xp-tlmm-state: 51 type: object 52 description: 53 Pinctrl node's client devices use subnodes for desired pin configuration. 54 Client device subnodes use below standard properties. 55 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state 56 57 properties: 58 pins: 59 description: 60 List of gpio pins affected by the properties specified in this 61 subnode. 62 items: 63 oneOf: 64 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$" 65 - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ] 66 minItems: 1 67 maxItems: 16 68 69 function: 70 description: 71 Specify the alternative function to be configured for the specified 72 pins. 73 74 enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, cci_i2c, 75 cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, 76 cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9, 77 cmu_rng, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, 78 ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, 79 ddr_pxi6, ddr_pxi7, dp2_hot, dp3_hot, edp0_lcd, edp1_lcd, 80 edp2_lcd, edp3_lcd, edp_hot, emac0_dll, emac0_mcg0, emac0_mcg1, 81 emac0_mcg2, emac0_mcg3, emac0_phy, emac0_ptp, emac1_dll0, 82 emac1_dll1, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3, 83 emac1_phy, emac1_ptp, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4, 84 gcc_gp5, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, ibi_i3c, 85 jitter_bist, lpass_slimbus, mdp0_vsync0, mdp0_vsync1, 86 mdp0_vsync2, mdp0_vsync3, mdp0_vsync4, mdp0_vsync5, 87 mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, mdp1_vsync0, 88 mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4, 89 mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync, 90 mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s1_data0, 91 mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, mi2s2_data1, 92 mi2s2_sck, mi2s2_ws, mi2s_mclk1, mi2s_mclk2, pcie2a_clkreq, 93 pcie2b_clkreq, pcie3a_clkreq, pcie3b_clkreq, pcie4_clkreq, 94 phase_flag, pll_bist, pll_clk, prng_rosc0, prng_rosc1, 95 prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qspi, qspi_clk, 96 qspi_cs, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, 97 qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17, 98 qup18, qup19, qup20, qup21, qup22, qup23, rgmii_0, rgmii_1, 99 sd_write, sdc40, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig, 100 tgu, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, 101 usb0_dp, usb0_phy, usb0_sbrx, usb0_sbtx, usb0_usb4, usb1_dp, 102 usb1_phy, usb1_sbrx, usb1_sbtx, usb1_usb4, usb2phy_ac, 103 vsense_trigger ] 104 105 bias-disable: true 106 bias-pull-down: true 107 bias-pull-up: true 108 drive-strength: true 109 input-enable: true 110 output-high: true 111 output-low: true 112 113 required: 114 - pins 115 116 additionalProperties: false 117 118examples: 119 - | 120 #include <dt-bindings/interrupt-controller/arm-gic.h> 121 pinctrl@f100000 { 122 compatible = "qcom,sc8280xp-tlmm"; 123 reg = <0x0f100000 0x300000>; 124 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 125 gpio-controller; 126 #gpio-cells = <2>; 127 interrupt-controller; 128 #interrupt-cells = <2>; 129 gpio-ranges = <&tlmm 0 0 230>; 130 131 gpio-wo-subnode-state { 132 pins = "gpio1"; 133 function = "gpio"; 134 }; 135 136 uart-w-subnodes-state { 137 rx-pins { 138 pins = "gpio4"; 139 function = "qup14"; 140 bias-pull-up; 141 }; 142 143 tx-pins { 144 pins = "gpio5"; 145 function = "qup14"; 146 bias-disable; 147 }; 148 }; 149 }; 150... 151