xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/qcom,sc8180x-tlmm.yaml (revision 7fdf597e96a02165cfe22ff357b857d5fa15ed8a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SC8180X TLMM block
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm SC8180X SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sc8180x-tlmm
21
22  reg:
23    maxItems: 3
24
25  reg-names:
26    items:
27      - const: west
28      - const: east
29      - const: south
30
31  interrupts:
32    maxItems: 1
33
34  gpio-reserved-ranges: true
35
36patternProperties:
37  "-state$":
38    oneOf:
39      - $ref: "#/$defs/qcom-sc8180x-tlmm-state"
40      - patternProperties:
41          "-pins$":
42            $ref: "#/$defs/qcom-sc8180x-tlmm-state"
43        additionalProperties: false
44
45$defs:
46  qcom-sc8180x-tlmm-state:
47    type: object
48    description:
49      Pinctrl node's client devices use subnodes for desired pin configuration.
50      Client device subnodes use below standard properties.
51    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
52    unevaluatedProperties: false
53
54    properties:
55      pins:
56        description:
57          List of gpio pins affected by the properties specified in this
58          subnode.
59        items:
60          oneOf:
61            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$"
62            - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
63        minItems: 1
64        maxItems: 16
65
66      function:
67        description:
68          Specify the alternative function to be configured for the specified
69          pins.
70
71        enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens,
72                atest_tsens2, atest_usb0, atest_usb1, atest_usb2, atest_usb3,
73                atest_usb4, audio_ref, btfm_slimbus, cam_mclk, cci_async,
74                cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
75                cci_timer4, cci_timer5, cci_timer6, cci_timer7, cci_timer8,
76                cci_timer9, cri_trng, dbg_out, ddr_bist, ddr_pxi, debug_hot,
77                dp_hot, edp_hot, edp_lcd, emac_phy, emac_pps, gcc_gp1, gcc_gp2,
78                gcc_gp3, gcc_gp4, gcc_gp5, gpio, gps, grfc, hs1_mi2s, hs2_mi2s,
79                hs3_mi2s, jitter_bist, lpass_slimbus, m_voc, mdp_vsync,
80                mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4,
81                mdp_vsync5, mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1,
82                pci_e2, pci_e3, phase_flag, pll_bist, pll_bypassnl, pll_reset,
83                pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss_gpio, qlink,
84                qspi0, qspi0_clk, qspi0_cs, qspi1, qspi1_clk, qspi1_cs,
85                qua_mi2s, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
86                qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
87                qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii, sd_write, sdc4,
88                sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu,
89                tsense_pwm1, tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
90                usb0_phy, usb1_phy, usb2phy_ac, vfr_1, vsense_trigger,
91                wlan1_adc, wlan2_adc, wmss_reset ]
92
93    required:
94      - pins
95
96required:
97  - compatible
98  - reg
99  - reg-names
100
101unevaluatedProperties: false
102
103examples:
104  - |
105    #include <dt-bindings/interrupt-controller/arm-gic.h>
106    pinctrl@3100000 {
107        compatible = "qcom,sc8180x-tlmm";
108        reg = <0x03100000 0x300000>,
109              <0x03500000 0x700000>,
110              <0x03d00000 0x300000>;
111        reg-names = "west", "east", "south";
112        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
113        gpio-controller;
114        #gpio-cells = <2>;
115        interrupt-controller;
116        #interrupt-cells = <2>;
117        gpio-ranges = <&tlmm 0 0 190>;
118
119        gpio-wo-subnode-state {
120            pins = "gpio1";
121            function = "gpio";
122        };
123
124        uart-w-subnodes-state {
125            rx-pins {
126                pins = "gpio4";
127                function = "qup6";
128                bias-pull-up;
129            };
130
131            tx-pins {
132                pins = "gpio5";
133                function = "qup6";
134                bias-disable;
135            };
136        };
137    };
138...
139